Mask and method for making the same, and method for making...

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S708000, C438S942000, C430S005000, C430S312000

Reexamination Certificate

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06955993

ABSTRACT:
A mask capable of alignment by the TTR system and complementary division and having a high strength, a method of production of the same, and a method of production of a semiconductor device having a high pattern accuracy are provided. A stencil mask having stripe-shaped grid lines4formed by etching a silicon wafer in four sub-regions A to D on a membrane, having the stripes arranged point symmetrically about a center of the membrane, and having all of the grid lines connected to other grid lines or the silicon wafer around the membrane (support frame), a method of production of the same, and a method of production of a semiconductor device using the mask.

REFERENCES:
patent: 5849437 (1998-12-01), Yamazaki et al.
patent: 6376137 (2002-04-01), Okino
patent: 2001/0046631 (2001-11-01), Fujiwara et al.
patent: 61-283121 (1986-12-01), None
patent: 7-312341 (1995-11-01), None
patent: 8-202018 (1996-08-01), None
patent: 2001-332468 (2000-05-01), None
patent: 2000-323372 (2000-11-01), None
patent: 2000-357647 (2000-12-01), None
patent: 2001-052989 (2001-02-01), None
patent: 2003-059819 (2003-02-01), None

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