Data processing: structural design – modeling – simulation – and em – Simulating electronic device or electrical system – Circuit simulation
Reexamination Certificate
2006-02-28
2006-02-28
Homere, Jean R. (Department: 2128)
Data processing: structural design, modeling, simulation, and em
Simulating electronic device or electrical system
Circuit simulation
C703S013000, C703S014000, C703S019000, C716S030000, C716S030000
Reexamination Certificate
active
07006961
ABSTRACT:
A design tool and method characterizes a circuit at a hardware level description. A behavioral level description of the circuit is created. Symbolic equations for components of the behavioral level description are created. The behavioral level description is partitioned by inserting a marker component into the behavioral level description of the circuit to simplify subsequent processing used to prove equivalence between the behavioral and hardware level descriptions. The symbolic equations are back-substituted until output variables are expressed in terms of input variables that determine the output variables. The marker component is defined using a unique symbolic name. Current time counts of each clock cycle are used to compute an index for the marker component. The behavioral level description is transformed to produce symbolic and numeric files for compilation to gates and proof of functionality.
REFERENCES:
patent: 5222030 (1993-06-01), Dangelo et al.
patent: 5526277 (1996-06-01), Dangelo et al.
patent: 5541849 (1996-07-01), Rostoker et al.
patent: 5544066 (1996-08-01), Rostoker et al.
patent: 5544067 (1996-08-01), Rostoker et al.
patent: 5557531 (1996-09-01), Rostoker et al.
patent: 5572437 (1996-11-01), Rostoker et al.
patent: 5655107 (1997-08-01), Bull
patent: 5867399 (1999-02-01), Rostoker et al.
patent: 5870308 (1999-02-01), Dangelo et al.
patent: 5933356 (1999-08-01), Rostoker et al.
patent: 6026219 (2000-02-01), Miller et al.
patent: 6077303 (2000-06-01), Mandell et al.
patent: 6182258 (2001-01-01), Hollander
patent: 6421815 (2002-07-01), Seawright
patent: 6424962 (2002-07-01), Billon
patent: 6470482 (2002-10-01), Rostoker et al.
patent: 6477698 (2002-11-01), Shalish
patent: 6513143 (2003-01-01), Bloom et al.
patent: 6691079 (2004-02-01), Lai et al.
patent: 6701494 (2004-03-01), Giddens et al.
patent: 6745160 (2004-06-01), Ashar et al.
patent: 6757884 (2004-06-01), Mandell et al.
patent: 6782511 (2004-08-01), Frank et al.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 901665, Product: Behavioral Compiler, Topic: “use—netlist attribute with preserve function” Last Updated: Oct. 23, 1998.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 901157, Product: Behavioral Compiler, Topic: “Using Preserved Functions in Behavioral Compiler” Last Updated: Oct. 16, 2001.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 002613, Product: (V)HDL Compiler, Topic: “Verilog and VHDL Directives” Last Updated: Oct. 8, 2002.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 901336, Product: Design Compiler, Topic: “The partition—dp command does not work on a Mapped Design” Last Updated: Aug. 2, 2001.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 901884, Product: Design Compiler, Topic: “Case Selector Bit Ranges Not Valid” Last Updated: Nov. 14, 2000.
https://solvnet.synopsys.com; Synopsys Solvit Doc Id: 903912, Product: Design Compiler, Topic: “Behavioral Compiler Information Roadmap” Last Updated: Oct. 23, 2001.
“Computer-Aided Partitioning of Behavioral Hardware”, McFarland, M.C., S.J. This paper appears in: IEEE, Design Automation Conference Proceedings 1983, 20th, pp. 472-478□□.
“Assignment Decision Diagram and its Uses in High-level Synthesis”, V. Chaiyakul and D.D. Gajski, Technical Report 190 9˜-103, University of California Irvine, Oct. 1992.
“Heirarchial Model Partitioning for Parallel VLSI-Simulation Using Evolutionary Algorithms Improved By Superpositions of Partitions” by Haupt R. et al; Proc. 5th European Conr. on Intell. Techn. and Soft Comp. (EUFIT'97), p. 804-808, 1997.
“Computer-Aided Partitioning of Behavioral Hardware”, McFarland, M.C., S.J. This paper appears in: IEEE, Design Automation Conference Proceedings 1983, 20th, pp. 472-478.
“Assignment Decision Diagram and its Uses in High-level Synthesis”, V. Chaiyakul and D.D. Gajski, Technical Report #9˜-103, University of California Irvine, Oct. 1992.
Berman Arnold L.
Mandell Michael I.
Harness & Dickey & Pierce P.L.C.
Homere Jean R.
Saxena Akash
The Boeing Company
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