Mark structure for coarse wafer alignment and method for...

Details Mark structure for coarse wafer alignment and method for... Mark structure for coarse wafer alignment and method for...

2011-08-02

2011-08-02

Lee, Calvin (Department: 2892)

Active solid-state devices (e.g., transistors, solid-state diode

Alignment marks

C438S401000, C438S462000

Reexamination Certificate

active

07989966

ABSTRACT:
A mark structure includes on a substrate, at least four lines. The lines extend parallel to each other in a first direction and are arranged with a pitch between each pair of lines that is directed in a second direction perpendicular to the first direction. The pitch between each pair of selected lines differs from the pitch between each other pair of selected lines.

REFERENCES:
patent: 7319506 (2008-01-01), Den Boef et al.
patent: 7332732 (2008-02-01), Van Bilsen et al.
patent: 7863763 (2011-01-01), Van Haren et al.
patent: 2007/0114678 (2007-05-01), Van Haren et al.
patent: 1 372 040 (2003-12-01), None
patent: 10-0777417 (2007-11-01), None
English translation of Korean Office Action mailed Nov. 5, 2010, directed to related Korean Application No. 10-2009-0012777, Korean Intellectual Property Office; 3 pages.

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