Mark protection with transparent film

Details Mark protection with transparent film Mark protection with transparent film

1998-12-04

2001-03-27

Lee, John R. (Department: 2878)

Radiant energy

Photocells; circuits and apparatus

Photocell controls its own optical systems

C356S399000, C438S401000

Reexamination Certificate

active

06207966

ABSTRACT:

FIELD OF THE INVENTION
The present invention generally relates to lithography and more particularly relates to a structure for protecting alignment marks on a substrate. The protection structure protects the integrity of the alignments marks during various forms of processing, thus enabling alignment to be maintained throughout processing, and minimizing registration errors.
BACKGROUND OF THE INVENTION
In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities there has been, and continues to be, efforts toward scaling down the device dimensions on semiconductor wafers. In order to accomplish such a high device packing density, smaller features sizes are required. This may include the width and spacing of interconnecting lines and the surface geometry such as the comers and edges of various features.
The requirement of small features with close spacing between adjacent features requires high resolution photolithographic processes. In general, lithography refers to processes for pattern transfer between various media. It is a technique used for integrated circuit fabrication in which, for example, a silicon wafer is coated uniformly with a radiation-sensitive film (e.g., a photoresist), and an exposing source (such as ultraviolet light, x-rays, or an electron beam) illuminates selected areas of the film surface through an intervening master template (e.g., a mask or reticle) to generate a particular pattern. The exposed pattern on the photoresist film is then developed with a solvent called a developer which makes the exposed pattern either soluble or insoluble depending on the type of photoresist (i.e., positive or negative resist). The soluble portions of the resist are then removed, thus leaving a photoresist mask corresponding to the desired pattern on the silicon wafer for further processing.
Clearly, projection lithography is a powerful and important tool for integrated circuit processing. However, in order to further increase the packing density of integrated circuits, not only is the quality of lithographic imaging important, but the accuracy with which an image can be positioned on the surface of a substrate is also of considerable importance. Because integrated circuits are fabricated by patterning a plurality of layers in a particular sequence to generate features that require a particular spatial relationship with respect to one another, each layer must be properly aligned with respect to previously patterned layers to minimize the size of individual devices and thus maximize the packing density on the substrate. Presently, having a perfect overlap (i.e., zero registration error) is not easily achievable. Consequently, a registration or overlay tolerance is required between two layers to ensure reliability in the construction of the resulting device. This registration or overlay tolerance undesirably increases the size of various structures and therefore attempts are made to minimize the tolerance.
As is evident from the discussion above, it is desirable to minimize the registration tolerance needed to form overlying patterns in order to improve the packing density of structures which form the integrated circuit. One solution which has been used to maximize the pattern overlay accuracy of various layers is to form one or more alignment marks or patterns on the underlying substrate and each mask. When the alignment marks or patterns on the substrate and mask are optically aligned, for example, then the remainder of the circuit patterns are assumed to be aligned.
Another type of alignment system uses an alignment mark scheme as illustrated in prior art
FIG. 1
, which illustrates a fragmentary cross section of a substrate such as a silicon wafer. A substrate
50
has one or more recesses
52
formed therein which serve as alignment marks. Each recess preferably has a depth
54
which is a function of the alignment radiation wavelength (e.g., a depth of &lgr;/4). The predetermined depth
54
provides a destructive interference phenomena upon the reflection off the marks
52
which allows the alignment marks
52
to be more effectively “seen” (i.e., they exhibit a better reflective contrast than the neighboring non-recessed regions and are thus more visible).
An exemplary prior art alignment system
58
uses the alignment marks
52
of prior art
FIG. 1
in the following manner, as illustrated in prior art FIG.
2
. An alignment light source (not shown) illuminates a grating of alignment marks
52
with radiation
60
which has its diffracted orders reflect off the alignment marks
52
and get captured by a lens
62
and directed toward a mask
64
. The reflected radiation
60
is used as a signal to detect the alignment between the mask
64
and the substrate
50
.
As will become apparent in the discussion that follows, the prior art alignment mark structure suffers from some disadvantages which prevents alignment accuracy from being maximized. There is thus a need in the art for improved alignment structures and systems.
SUMMARY OF THE INVENTION
The present invention relates to an alignment mark protection structure which protects an alignment mark from process-induced damage. Consequently, the integrity of the alignment mark is preserved throughout a range of processing steps, thereby maintaining optimal alignment between a mask and the substrate throughout processing and thus minimizing registration error among various layers formed during such processing.
According to one aspect of the present invention, the alignment mark protection structure includes an alignment mark associated with a substrate on which and/or within which processing is to occur. A cap is formed over the alignment mark to thereby protect the alignment mark during various forms of processing such as etching, stripping, cleaning, polishing, etc. The cap is substantially transparent with respect to an alignment light and therefore does not impact the alignment accuracy of the alignment mark over the prior art. Instead, the alignment mark protection structure of the present invention improves the alignment accuracy over prior art alignment schemes by preventing the formation of foreign matter within the alignment mark during processing, thus eliminating the denigration in alignment due to noise within the reflected alignment light.
According to another aspect of the present invention, the alignment mark is formed in a non-active region of the substrate. The alignment mark preferably constitutes a recess having a rectangular cross section with a depth that is about one-quarter of the wavelength of the alignment light (&lgr;/4) in order to maximize the reflection contrast of the alignment light at the alignment mark with respect to the surrounding region, thus allowing the mark to be more easily “seen”. Alternatively, the alignment mark may constitute a projection having a rectangular cross section with a height that is a function of the alignment wavelength (e.g., &lgr;/4) for optimal contrast. In addition, the cap may comprise one or more layers which are substantially transparent with respect to the alignment light. During processing, an exposed surface of the cap may receive process-induced damage. However, such damage on the surface of the cap is typically of a random nature and thus can be filtered; consequently such damage on the cap does not impact the alignment accuracy. Consequently, the cap prevents the formation of foreign matter within or on the alignment mark during processing and provides for an accurate alignment scheme throughout multiple processing steps.


REFERENCES:
patent: 4487653 (1984-12-01), Hatcher
patent: 4595295 (1986-06-01), Wilczynski
patent: 4712016 (1987-12-01), Matsumura
patent: 5128283 (1992-07-01), Tanaka
patent: 5407763 (1995-04-01), Pai
patent: 5570405 (1996-10-01), Chan et al.
patent: 5738961 (1998-04-01), Chen
patent: 5801090 (1998-09-01), Wu et al.
patent: 5824441 (1998-10-01), Farrow et al.
patent: 6057206 (2000-05-01), Nguyen et al.
“Lithography II: Optical Aligners and Photomasks”, Silicon Proce

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