Data processing: measuring – calibrating – or testing – Measurement system – Measured signal processing
Reexamination Certificate
2002-01-29
2004-02-10
Bui, Bryan (Department: 2863)
Data processing: measuring, calibrating, or testing
Measurement system
Measured signal processing
C369S047260
Reexamination Certificate
active
06691072
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to an apparatus and a method for selecting mark lengths of a signal which is read from an optical disc, and an apparatus and a method for detecting a maximum mark length.
BACKGROUND OF THE INVENTION
As a method for generating a clock for reading data from a recording medium such as an optical disc, there has generally been employed a method of generating a clock for reading data by comparing the clock and the data frequency, and performing control to make the both have the same frequency.
FIG. 6
is a block diagram illustrating the structure of an apparatus for generating a clock for reading data.
With reference to
FIG. 6
, a maximum mark length detection unit
200
detects a maximum mark length D
201
within a certain period of time, among mark lengths of data D
200
which have been read from an optical disc by an optical pickup, and outputs the maximum mark length D
201
. A mark length is the length of continuous 0s or 1s included in data. For example, in a sequence {1111110001111}, the respective mark lengths are 6T, 3T, and 4T (T: cycle).
A PLL (Phase Locked Loop)
201
generates a read clock D
202
which is a clock for reading data. The frequency of the read clock D
202
varies according to a control pulse D
204
supplied from a frequency comparator
203
.
A frequency divider
202
multiplies the cycle of the read clock D
202
by an integer, thereby to frequency-divide the read clock D
202
.
A frequency comparator
203
compares the length (cycle) of the maximum mark length D
201
with the length of one cycle of the clock D
203
that is frequency-divided by the frequency divider
202
, and outputs a control pulse D
204
to the PLL
201
to make these lengths equal.
A playback signal processing unit
204
performs demodulation, gate signal processing and the like, on the data D
200
.
Next, the operation of the clock generation apparatus will be described.
Initially, the data D
200
which is binarized into 0s or 1s with respect to an RF signal reproduced from the optical disc is inputted to the maximum mark length detection unit
200
, and the mark lengths in the data D
200
are successively counted with a fixed clock. When a predetermined period of time has passed, a maximum mark length is detected.
In the data format of a DVD-ROM, a maximum mark length is a width of 14T, in which 14 pieces of 0s or 1s are arranged. Further, as shown in
FIG. 7
, a pattern of 14T+4T(=18T) existing in the binary data D
200
is called a sync pattern, and this is a specific mark existing in every frame (a minimum unit in which data are written: 1 frame=1488T).
That is, when detection of a maximum mark length is carried out within a predetermined period of time that is longer than one frame, the detected maximum mark length has a width of 14T.
The outputted maximum mark length D
201
is inputted to the frequency comparator
203
. On the other hand, the read clock D
202
outputted from the PLL
201
is frequency-divided by the frequency divider
202
so that it may be compared with the frequency (cycle) of the maximum mark length D
201
. That is, when the maximum mark length is 14T, the read clock D
202
is frequency-divided so that its cycle is multiplied by 14. The cycle (frequency) of the maximum mark length D
201
and the cycle (frequency) of the frequency-divided clock D
203
are compared by the frequency comparator
203
. When the cycle of the maximum mark length D
201
is shorter than the cycle of the frequency-divided clock D
203
(i.e., when the frequency of the maximum mark length D
201
is higher than the frequency of the clock D
203
), the frequency comparator
203
outputs a frequency control pulse D
204
for increasing the frequency of the read clock D
202
. When the cycle of the maximum mark length D
201
is longer than the cycle of the frequency-divided clock D
203
(i.e., when the frequency of the maximum mark length D
201
is lower than the frequency of the clock D
203
), the comparator
203
outputs a frequency control pulse D
204
for reducing the frequency of the read clock D
202
.
By performing the above-mentioned control, the read clock D
202
can always be maintained at the frequency according to the data frequency.
Using the read clock D
202
so generated, the playback signal processing unit
204
reads the binary data D
200
, and subjects the binary data D
200
to demodulation, gate signal processing, and the like.
The read clock D
202
in
FIG. 7
shows its controlled state. Although the read clock D
202
does not match the frequency of the data D
200
before performing the above-mentioned control, the read clock D
202
matches the frequency of the data D
200
after the control has been continued.
Next, the maximum mark length detection unit
200
will be described.
As a method for detecting a maximum mark length, the maximum mark length detection apparatus
200
usually employs a method as follows. That is, a mark length is measured, and the measured mark length is compared with a previously detected maximum mark length. When the measured mark length is longer than the maximum mark length, the measured mark length is stored in a register as a latest maximum mark length. On the other hand, when the measured mark length is shorter than the previous maximum mark length, the value stored in the register is maintained. By employing this method, the value stored in the register is always the maximum mark length.
FIG. 8
is a block diagram illustrating the structure of the conventional maximum mark length detection apparatus.
With reference to
FIG. 8
, a mark length measuring unit
100
measures a mark length of a binary signal which is read from the optical disc. A maximum mark length storage register
101
stores the measured mark length D
100
on the basis of a write enable signal D
102
, and outputs a stored maximum mark length D
101
. A comparator
102
a
compares the measured mark length D
100
with the maximum mark length D
101
, and outputs the write enable signal D
102
to the maximum mark length storage register
101
when the measured mark length D
100
is longer than the maximum mark length D
101
.
Next, the operation of the maximum mark length detection unit
200
will be described.
Initially, an RF signal outputted from the optical disc is binarized, and the binary signal is inputted to the mark length measuring unit
100
. Then, a mark length is measured, and a measured mark length D
100
indicating the measured mark length is outputted.
The comparator
102
a
compares the measured mark length D
100
with the maximum mark length D
101
stored in the maximum mark length storage register
101
, and outputs a write enable signal D
102
to the maximum mark length storage register
101
when the measured mark length D
100
is longer than the maximum mark length D
101
(i.e., when measured mark length D
100
>maximum mark length D
101
). Then, the maximum mark length storage register
101
stores the measured mark length D
100
. In the comparison by the comparator
102
a,
when the maximum mark length D
101
is longer than the measured mark length D
100
, the comparator
102
outputs no write enable signal D
102
. Accordingly, the maximum mark length storage register
101
does not store the measured mark length D
100
, and the value stored in the maximum mark length storage register
101
is maintained.
In this way, the maximum mark length storage register
101
always holds the maximum mark length among the mark lengths which have previously been measured by the mark length measuring unit
100
, and outputs the maximum mark length D
101
.
FIG. 9
is a timing chart for explaining the operation of the conventional maximum mark length detection unit.
For example, since the maximum mark length D
101
is “5” when the measured mark length D
100
is “11”, the comparator
102
a
judges that D
100
>D
101
, and outputs a write enable signal D
102
. That is, the write enable signal D
102
becomes high as shown in FIG.
9
. Then, the maximum mark length storage register
101
captures “
Fuke Akihiro
Tamura Yushi
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