Coded data generation or conversion – Converter calibration or testing
Reexamination Certificate
2003-03-14
2004-09-07
Wamsley, Patrick (Department: 2819)
Coded data generation or conversion
Converter calibration or testing
C341S135000
Reexamination Certificate
active
06788229
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to voltage level control circuits, and is particularly directed to a voltage margin setting interface circuit having a single input pin, and being operative to program the slew rate and polarity direction of variation of the operation of a digital-to-analog converter (DAC), such as may be used to set a reference voltage level, for application to an error amplifier of a voltage regulator circuit of the power supply for a microprocessor.
BACKGROUND OF THE INVENTION
The technique of varying the voltage to various controller integrated circuits is termed ‘power margining’. This technique has become increasingly important for the portable computer market, where the processor voltage is controllably increased depending upon operational demands. For example, the power may be decreased during low processing requirements, to result in a reduction in standby power. In a complementary manner, when there is a need for faster signal processing, for example, in graphics processing applications, processor speed must be increased to handle rapid or complex display changes. Associated with this increase in processor speed, the supply voltage is also increased to accommodate temporary high performance and power demands. On the other hand, when there is no need for speed, the power to the processor is reduced by way of a lower processor voltage, resulting in improved power supply economy.
SUMMARY OF THE INVENTION
With this objective in mind, the present invention is directed to a new and improved power margining interface, that is configured to provide on-demand adjustment, by means of a single input pin, of a reference voltage supplied by a digital-to-analog converter (DAC). For this purpose, the invention has an input port, to which an input or control voltage is supplied by way of an input scaling resistor, which converts the input voltage to an input current. This input current is coupled to an operational amplifier, which may be configured as an inverting unity gain buffer, referenced to a voltage midway between the range of input voltage variation.
The output of the operational amplifier is coupled through an output resistor to a pair of transmission gates. It is also directly coupled to an ‘increment DAC’ comparator and to a ‘decrement DAC’ comparator. These comparators control whether the DAC is either incremented or decremented, and also controllably close one of the transmission gates, and thereby steer a control current to a clock oscillator that clocks the DAC, with the absolute value of the control current defining the slew rate of the DAC.
The ‘increment DAC’ comparator operates so as to controllably increment the DAC in response to the comparator input voltage lying within a lower portion of the input voltage range, which is at least a prescribed offset above the voltage reference of the operational amplifier. Conversely, the ‘decrement DAC’ comparator operates so as to controllably cause the DAC to be decremented, in response to the comparator input voltage lying within an upper portion of the input voltage range that is at least the prescribed offset below the voltage reference of the operational amplifier.
The output of the increment comparator is coupled to a control input of one transmission gate and to a first output port which is coupled to the increment control input of the DAC. The output of the other comparator is coupled to a control input of the other transmission gate and to a second output port, which is coupled to the decrement input of the DAC. The outputs of the transmission gates are coupled to current mirror amplifiers that are configured to provide an output current that is the absolute value of their input currents.
In operation, as long as the input voltage is within the prescribed voltage offset, neither comparator is triggered and the margining pin interface circuit has no effect on the operation of the DAC, and the reference voltage delivered thereby. When it is desired to increase the reference voltage from the DAC, the input port to the respective comparator is supplied with a voltage having a value that is at least equal to the prescribed offset below the reference voltage. This causes the output of the ‘increment DAC’ comparator to change state, which places the DAC in increment mode, and causes so the DAC's reference voltage to be incremented at a clock rate that is determined by the value of the current being supplied by the absolute value circuit. The closer the input voltage to the ‘increment DAC’ comparator is to the lower end of the voltage range (namely the larger the difference between the input voltage and reference voltage to the ‘increment DAC’ comparator), the larger the current supplied to the absolute value circuit, causing the frequency of the clock rate for the DAC to be decreased by a relatively large amount. The absolute value circuit is configured to “sink” current from the oscillator, thus reducing oscillator frequency. On the other hand, the closer the input voltage is to the midpoint of the voltage range, the smaller the current supplied to the absolute value circuit, so that the clock rate for the DAC will be decreased by a relatively slower amount.
When it is desired to decrease the reference voltage supplied by the DAC, the input port of the comparator is supplied with a voltage that is the prescribed voltage above the reference voltage. This causes the output of the ‘decrement DAC’ comparator to change state, which places the DAC in the decrement mode, and causes the output reference voltage to be decremented at a clock rate determined by the value of the current being supplied by the absolute value circuit. The closer the input voltage is to the upper end of the voltage range (namely the larger the difference between the input voltage and the reference voltage to the ‘decrement DAC’ comparator), the larger the current supplied to the absolute value circuit, so that the DAC's clock frequency will be decreased by a relative large amount. On the other hand, the closer the input voltage is to the midpoint of the voltage range, the smaller the current supplied to the absolute value circuit, causing the DAC's clock to be decreased by a relatively small amount.
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Allen Dyer Doppelt Milbrath & Gilchrist, P.A.
Intersil America's Inc.
Wamsley Patrick
LandOfFree
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