Pulse or digital communications – Equalizers
Reexamination Certificate
2004-03-31
2009-12-01
Perilla, Jason M. (Department: 2611)
Pulse or digital communications
Equalizers
C375S230000, C375S231000, C375S232000, C375S233000, C375S234000, C375S235000, C375S236000, C375S353000, C327S050000
Reexamination Certificate
active
07627029
ABSTRACT:
Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data, and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns, and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.
REFERENCES:
patent: 3895349 (1975-07-01), Robson
patent: 4397029 (1983-08-01), Satorius et al.
patent: 4449102 (1984-05-01), Frazer
patent: 4475210 (1984-10-01), Couch
patent: 4695969 (1987-09-01), Sollenberger
patent: 4727540 (1988-02-01), Lacroix
patent: 4823026 (1989-04-01), Hanson
patent: 5191462 (1993-03-01), Gitlin et al.
patent: 5197062 (1993-03-01), Picklesimer
patent: 5228042 (1993-07-01), Gauthier et al.
patent: 5325397 (1994-06-01), Scholz et al.
patent: 5331663 (1994-07-01), Kurokami
patent: 5369755 (1994-11-01), Berkovich
patent: 5459762 (1995-10-01), Wang et al.
patent: 5475710 (1995-12-01), Ishizu et al.
patent: 5483676 (1996-01-01), Mahany
patent: 5499268 (1996-03-01), Takahashi
patent: 5539774 (1996-07-01), Nobakht et al.
patent: 5602602 (1997-02-01), Hulyalkar
patent: 5732089 (1998-03-01), Negi
patent: 5761212 (1998-06-01), Foland, Jr.
patent: 5761216 (1998-06-01), Sotome
patent: 5802073 (1998-09-01), Platt
patent: 5896392 (1999-04-01), Ono et al.
patent: 5917856 (1999-06-01), Torsti
patent: 5949819 (1999-09-01), Bjarnason et al.
patent: 5966262 (1999-10-01), Brickner et al.
patent: 5999022 (1999-12-01), Iwata
patent: 6003118 (1999-12-01), Chen
patent: 6016379 (2000-01-01), Bulow
patent: 6031866 (2000-02-01), Oler et al.
patent: 6055297 (2000-04-01), Terry
patent: 6154659 (2000-11-01), Jalali
patent: 6160790 (2000-12-01), Bremer
patent: 6222380 (2001-04-01), Gerowitz et al.
patent: 6230022 (2001-05-01), Sakoda
patent: 6256342 (2001-07-01), Schlag et al.
patent: 6289045 (2001-09-01), Hasegawa
patent: 6292116 (2001-09-01), Wang
patent: 6295152 (2001-09-01), Wedding
patent: 6307883 (2001-10-01), Kanada et al.
patent: 6307884 (2001-10-01), Du et al.
patent: 6331787 (2001-12-01), Whitworth
patent: 6339387 (2002-01-01), Koga
patent: 6378079 (2002-04-01), Mullarkey
patent: 6421801 (2002-07-01), Maddux
patent: 6430715 (2002-08-01), Myers et al.
patent: 6459727 (2002-10-01), Cho et al.
patent: 6459728 (2002-10-01), Bar-David et al.
patent: 6493394 (2002-12-01), Tamura et al.
patent: 6606041 (2003-08-01), Johnson
patent: 6625769 (2003-09-01), Huott et al.
patent: 6631486 (2003-10-01), Komatsu
patent: 6650698 (2003-11-01), Liau
patent: 6671842 (2003-12-01), Phan et al.
patent: 6671847 (2003-12-01), Chao et al.
patent: 6674998 (2004-01-01), Prentice
patent: 6691260 (2004-02-01), Ueno
patent: 6816558 (2004-11-01), Piirainen et al.
patent: 6907065 (2005-06-01), Kim
patent: 6947480 (2005-09-01), Beale et al.
patent: 6987804 (2006-01-01), Buchali et al.
patent: 7027544 (2006-04-01), Vaucher
patent: 7130366 (2006-10-01), Phanse et al.
patent: 7184477 (2007-02-01), Haunstein et al.
patent: 7188261 (2007-03-01), Tobias et al.
patent: 7203257 (2007-04-01), Fimoff et al.
patent: 7254345 (2007-08-01), Suzaki et al.
patent: 2001/0016929 (2001-08-01), Bonneau
patent: 2001/0021987 (2001-09-01), Govindarajan et al.
patent: 2001/0031028 (2001-10-01), Vaucher
patent: 2001/0040922 (2001-11-01), Buchali et al.
patent: 2001/0043658 (2001-11-01), Voorman et al.
patent: 2001/0055335 (2001-12-01), Agazzi et al.
patent: 2002/0016932 (2002-02-01), Kushiyama
patent: 2002/0044618 (2002-04-01), Buchwald et al.
patent: 2002/0060820 (2002-05-01), Buchali
patent: 2002/0064241 (2002-05-01), Muellner et al.
patent: 2002/0073373 (2002-06-01), Nakao
patent: 2002/0085656 (2002-07-01), Lee et al.
patent: 2002/0131531 (2002-09-01), Matsumoto et al.
patent: 2002/0138800 (2002-09-01), Kim et al.
patent: 2002/0181575 (2002-12-01), Birru
patent: 2002/0194539 (2002-12-01), Ellis et al.
patent: 2002/0196883 (2002-12-01), Best et al.
patent: 2003/0007584 (2003-01-01), Wedding
patent: 2003/0043899 (2003-03-01), Lai
patent: 2003/0067975 (2003-04-01), Yamakura et al.
patent: 2003/0088818 (2003-05-01), Manning
patent: 2003/0095619 (2003-05-01), Vallet et al.
patent: 2003/0112909 (2003-06-01), Best
patent: 2003/0135768 (2003-07-01), Knee et al.
patent: 2003/0142740 (2003-07-01), Haunstein et al.
patent: 2003/0223489 (2003-12-01), Smee et al.
patent: 2004/0001566 (2004-01-01), Gregorius et al.
patent: 2004/0022337 (2004-02-01), Moll
patent: 2004/0032904 (2004-02-01), Orlik et al.
patent: 2004/0091041 (2004-05-01), Shanbhag et al.
patent: 2004/0114698 (2004-06-01), Barrett et al.
patent: 2004/0208266 (2004-10-01), Lenosky
patent: 2006/0132339 (2006-06-01), Alon
patent: 199 14 793 (2000-10-01), None
patent: 102 41 848 (2004-03-01), None
patent: 1 127 423 (2001-08-01), None
patent: 1134668 (2001-09-01), None
patent: 1 143 654 (2001-10-01), None
patent: 1 315 327 (2003-05-01), None
patent: WO 00/27065 (2000-05-01), None
patent: WO 02093821 (2002-11-01), None
Granberg, Tom, “Handbook of Digital Techniqus for High-Speed Design.” Prentice Hall Modern Semiconductor Design Series. Copyright 2004 by Pearson Education, Inc. 12 pages.
Maxfield, C., “The Ouroboros of the Digital Consciousness: Linear-Feedback-Shift Registers,” EDN, pp. 135-142, Jan. 4, 1996.
Dally et al., “Multi-gigabit Signaling with CMOS,” DARPA funded presentation, 22 pages, May 12, 1997.
Cova et al., Characterization of Individual Weights in Transversal Filters and Application to CCD's, IEEE Journal of Solid-State Circuits, vol. SC-17, No. 6, Dec. 1982, pp. 1054-1061.
Farber et al, “Wide-Band Network Characterization by Fourier Transformation of Time-Domain Measurements,” IEEE Journal of Solid-State Circuits, vol. SC-4, No. 4, Aug. 1969, pp. 231-235.
Soumyanath, K. et al, “Accurate On-Chip Interconnect Evaluation: A Time-Domain Technique.” IEEE Journal of Solid-State Circuits, vol. 34, No. 5, May 1999, pp. 623-631.
Sato, T., et al., “Accurate In Situ Measurement of Peak Noise and Delay Change Induced by Interconnect Coupling,” IEEE Journal of Solid-State Circuits, vol. 36, No. 10, Oct. 2001. pp. 1587-1591.
Ikawa, Y. et al, “Modeling of High-Speed, Large-Signal Transistor Switching Transcients from s-Parameter Measurements,” IEEE Journal of Solid-State Circuits, vol. SC-17, No. 2, Apr. 1982, pp. 299-305.
Klein, B., “Use LFSRs to Build Fast FPGA-Based Counters,” Electronic Design, pp. 87-100, Mar. 21, 1994.
Horowitz, Mark, “Lecture 15: Transmitter and Receiver Design.” Computer Systems Laboratory—Stanford University. Copyright 2000. pp. 15-1 to 15-35.
Cypress Semiconductor Coproration, “HOTLink™ Built-In Self-Test (BIST).” Mar. 11, 1999. 13 pages.
Pfaff, A., “Test high-speed drivers with bursts and pseudorandom bit patterns,” EDN, pp. 133-136, May 12, 1994 (3 pages).
Ellermeyer et al., “A 10-Gb/s Eye-Opening Monitor IC for Decision-Guided Adaptation of the Frequency Response of an Optical Receiver.” IEEE Journal of Solid-State Circuits, vol. 35, No. 12, Dec. 2000. pp. 1958-1963.
Stojanovic, Vladimir et al., “Modeling and Analysis of High-Speed Links.” Research supported by the MARCO Interconnect Focus Center and Rambus, Inc. 2003. 8 pages.
Kiran, Rajarshi Gupta, et al., “Computationally Efficient Version of the Decision Feedback Equalizer.” Sep. 1998. 4 Pages.
Degen, Christoph M. Degen, et al., “Comparative Study of Efficient Decision-Feedback Equalization Schemes for MIMO Systems.” Presented in Feb.
Chen Fred F.
Garlepp Bruno W.
Ho Andrew
Stojanovic Vladimir
Behiel Arthur J.
Perilla Jason M.
Rambus Inc.
Silicon Edge Law Group LLP
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