Mapping of gate arrays

Details Mapping of gate arrays Mapping of gate arrays

1996-03-15

1998-10-06

Teska, Kevin J.

Boots, shoes, and leggings

364488, 364489, G06F 1750

Patent

active

058187286

ABSTRACT:
This invention discloses a gate array device, useful either as a configurable gate array device or a compact gate array device, comprising an array of two-gate logic cells arranged in columns, a metal grid interconnecting said logic cells into clusters of macrocells, said grid comprising a bottom metal layer and at least one metal layer disposed over the bottom metal layer, power and ground lines formed of said bottom metal layer, extending generally parallel to said columns and a routing grid interconnecting said clusters of macrocells, said routing grid comprising parallel metal tracks crossing said columns of logic cells, and wherein no more than two of said parallel metal tracks are employed to connect to each logic cell.

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patent: 5563801 (1996-10-01), Lee et al.
De Micheli, "Technology Mapping of Digital Circuits," 5.sup.th Annual European Computer Conference, 1991, pp. 580-586.
Knapp, "Optimizing Programmable Gate Array Designs," 1988 Electro Conference, pp. 1-7.

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