Mapping communication in a parallel processing environment

Data processing: software development – installation – and managem – Software program development tool – Translation of code

Reexamination Certificate

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Reexamination Certificate

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07818725

ABSTRACT:
An the integrated circuit comprises a plurality of processor cores interconnected by an interconnection network. A method for generating instructions to be executed in the integrated circuit comprises accepting a plurality of programs, at least some of the programs including one or more communication operations to communicate with other programs; mapping each program to one or more of the processor cores; determining correspondence among communication operations in the programs; and mapping communication for corresponding communication operations to resources associated with the interconnection network.

REFERENCES:
patent: 7028281 (2006-04-01), Agrawal et al.
patent: 7394288 (2008-07-01), Agarwal
patent: 7461236 (2008-12-01), Wentzlaff
patent: 2004/0060032 (2004-03-01), McCubbrey
patent: 2004/0105384 (2004-06-01), Gallezot et al.
patent: 2004/0250046 (2004-12-01), Gonzalez et al.
patent: 2004/0268286 (2004-12-01), New et al.
patent: 2006/0179429 (2006-08-01), Eggers et al.
patent: 2006/0206850 (2006-09-01), McCubbrey
patent: WO 2004/072796 (2004-08-01), None
Weng et al., Profiling and mapping of parallel workloads on network processors, ACM, p. 890-896.
“Pipe.” The Single UNIX® Specification, Version 2, Copyright © 1997, The Open Group, pp. 1-2. Downloaded Nov. 29, 2006 from http://www.opengroup.org/onlinepubs/007908799/xsh/pipe.html.
Agarwal, Anant et al. “Mapping Communication in a Parallel Processing Environment”, U.S. Appl. No. 11/414,473, filed Apr. 28, 2006.
Wentzlaff, David. “Buffering Data in a Parallel Processing Environment”, U.S. Appl. No. 11/313,900, filed Dec. 21, 2005.
USPTO Non-final Office Action issued in U.S. Appl. No. 12/130,462, mailed Mar. 3, 2009, 8 pages.
USPTO Non-final Office Action issued in U.S. Appl. No. 11/404,187, mailed Feb. 5, 2009, 15 pages.
USPTO Non-final Office Action issued in U.S. Appl. No. 11/404,207, mailed Nov. 13, 2008, 9 pages.
USPTO Non-final Office Action issued in U.S. Appl. No. 11/404,655, mailed Mar. 23, 2009, 14 pages.
Agarwal, Anant. “Raw Computation,”Scientific Americanvol. 281, No. 2: 44-47, Aug. 1999.
Taylor, Michael Bedford et. al., “Evaluation of the Raw Microprocessor: An Exposed-Wire-Delay Architecture for ILP and Streams,”Proceedings of International Symposium on Computer Architecture, Jun. 2004.
Taylor, Michael Bedford et. al., “Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architectures,”Proceedings of the International Symposium on High Performance Computer Architecture, Feb. 2003.
Taylor, Michael Bedford et. al., “A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network,”Proceedings of the IEEE International Solid-State Circuits Conference, Feb. 2003.
Taylor, Michael Bedford et. al., “The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs,”IEEE Micro, pp. 25-35, Mar.-Apr. 2002.
Lee, Walter et. al., “Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine,”Proceedings of the Eighth International Conference on Architectural Support for Programming Languages and Operating Systems(ASPLOS-VIII), San Jose, CA, Oct. 4-7, 1998.
Kim, Jason Sungtae et. al., “Energy Characterization of a Tiled Architecture Processor with On-Chip Networks,”International Symposium on Low Power Electronics and Design, Seoul, Korea, Aug. 25-27, 2003.
Barua, Rajeev et. al., “Compiler Support for Scalable and Efficient Memory Systems,”IEEE Transactions on Computers, Nov. 2001.
Waingold, Elliot et. al., “Baring it all to Software: Raw Machines,”IEEE Computer, pp. 86-93, Sep. 1997.
Lee, Walter et. al., “Convergent Scheduling,”Proceedings of the 35thInternational Symposium on Microarchitecture, Istanbul, Turkey, Nov. 2002.
Wentzlaff, David and Anant Agarwal, “A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation,”MIT/LCS Technical Report LCS-TR-944, Apr. 2004.
Suh, Jinwoo et. al., “A Performance Analysis of PIM, Stream Processing , and Tiled Processing on Memory-Intensive Signal Processing Kernels,”Proceedings of the International Symposium on Computer Architecture, Jun. 2003.
Barua, Rajeev et. al., “Maps: A Compiler-Managed Memory System for Raw Machines,”Proceedings of the Twenty-Sixth International Symposium on Computer Architecture(ISCA-26), Atlanta, GA, Jun. 1999.
Barua, Rajeev et. al., “Memory Bank Disambiguation using Modulo Unrolling for Raw Machines,”Proceedings of the Fifth International Conference on High Performance Computing, Chennai, India, Dec. 17-20, 1998.
Agarwal, A. et. al., “The Raw Compiler Project,”Proceedings of the Second SUIF Compiler Workshop, Stanford, CA, Aug. 21-23, 1997.
Taylor, Michael Bedford et. al., “Scalar Operand Networks,”IEEE Transactions on Parallel and Distributed Systems(Special Issue on On-Chip Networks), Feb. 2005.
Taylor, Michael. The Raw Prototype Design Document V5.01 [online]. Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, Sep. 6, 2004 [retrieved on Sep. 25, 2006]. Retrieved from the Internet: <ftp://ftp.cag.Ics.mit.edu/pub/raw/documents/RawSpec99.pdf>.
Moritz, Csaba Andras et. al., “Hot Pages: Software Caching for Raw Microprocessors,”MIT/LCS Technical Memo LCS-TM-599, Aug. 1999.
Gordon, M. I. et al., “A Stream Compiler for Communication-Exposed Architectures.” MIT Laboratory for Computer Science, Cambridge, MA, 2002.
Agarwal, A. et al., “The MIT Alewife Machine: Architecture and Performance.” Massachusetts Institute of Technology. Cambridge, MA, 1995.
Rau, B. Ramakrishna, “Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops.” Hewlett-Packard Laboratories, 1994.
Gropp, William et al., “A High-Performance, Portable Implementation of the MPI Message Passing Interface Standard.” Mathematics and Computer Science Division, Argonne National Laboratory. Available from http://www-unix.mcs.anl.gov/mpi/mpichl/papers/mpichimpl.pdf before 2006).

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