Manufacturing self-aligned polysilicon fet devices isolated with

Details Manufacturing self-aligned polysilicon fet devices isolated with Manufacturing self-aligned polysilicon fet devices isolated with

1997-05-01

2000-08-15

Fourson, George

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

438692, 438699, 438734, H01L 2176

Patent

active

061035920

ABSTRACT:
FET devices are manufactured using STI on a semiconductor substrate coated with a pad from which are formed raised active silicon device areas and dummy active silicon mesas capped with pad structures on the doped silicon substrate and pad structure. A conformal blanket silicon oxide layer is deposited on the device with conformal projections above the mesas. Then a polysilicon film on the blanket silicon oxide layer is deposited with conformal projections above the mesas. The polysilicon film projections are removed in a CMP polishing step which continues until the silicon oxide layer is exposed over the pad structures. Selective RIE partial etching of the conformal silicon oxide layer over the mesas is next, followed in turn by CMP planarization of the conformal blanket silicon oxide layer which converts the silicon oxide layer into a planar silicon oxide layer, using the pad silicon nitride as an etch stop.

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J.-Y. Cheng, T.F. Lei, T.S. Chao, D.L.W.Yen, B.J. Jin, and C. J. Lin "A Novel Planarization of Oxide-Filled Shallow-Trench Isolation" J. Electrochem. Soc., vol. 144, No. 1, (Jan., 1997) pp. 315-320.

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