Fishing – trapping – and vermin destroying
Patent
1990-08-15
1991-06-11
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437 41, 437 62, 437 63, 437 64, 437 83, 437200, 437228, 437233, 148DIG51, 148DIG161, H01L 21265
Patent
active
050231979
ABSTRACT:
A method for manufacturing a MOS transistor formed in a silicon block on insulator with convex rounded up edges, initially consisting in etching the block in a thin layer of silicon on insulator (SOI). In this method etching of the block comprises the following steps: forming at the position where it is desired to obtain the block a mask layer portion (3) having a thickness slightly higher than that of the SOI; depositing a second silicon layer (11) having a predetermined thickness; and anisotropically etching silicon until said insulator is apparent outside the mask layer portion.
REFERENCES:
patent: 4349408 (1982-09-01), Tarng et al.
patent: 4394182 (1983-07-01), Maddox, III
patent: 4637836 (1987-01-01), Flatley et al.
patent: 4716128 (1987-12-01), Schubert et al.
patent: 4735679 (1988-04-01), Lasky
patent: 4753896 (1988-06-01), Matloubian
patent: 4903108 (1990-02-01), Young et al.
patent: 4906587 (1990-03-01), Blake
patent: 4916086 (1990-04-01), Takahashi et al.
Galvier Jean
Haond Michel
French State represented by the Minister of Post, Telecommunicat
Hearn Brian E.
Picardat Kevin
LandOfFree
Manufacturing process of mesa SOI MOS transistor does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing process of mesa SOI MOS transistor, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing process of mesa SOI MOS transistor will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-782448