Manufacturing process of a chip package structure

Details Manufacturing process of a chip package structure Manufacturing process of a chip package structure

2006-05-26

2009-11-24

Tran, Thien F (Department: 2895)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

C438S108000, C257S778000

Reexamination Certificate

active

07622326

ABSTRACT:
A manufacturing process of a chip package structure is provided. The manufacturing method uses fine pitch circuit processes, such as a TFT-LCD process or an IC process, to increase layout density and shorten electrical transmission pathways so that a higher electrical performance level is attained. First, a multi-layered interconnection structure with high-density bonding pads and fine pitch circuit is formed over a hard support base plate having a large area and high degree of planarity. A die is attached to a top surface of the multi-layered interconnection structure. A plurality of opening is formed on a bottom surface of the support base plate. Contacts are positioned into the openings in the support base plate such that the contacts are electrically connected to an inner circuit within the multi-layered interconnection structure.

REFERENCES:
patent: 5909058 (1999-06-01), Yano et al.
patent: 5982018 (1999-11-01), Wark et al.
patent: 6370013 (2002-04-01), Iino et al.
patent: 6583515 (2003-06-01), James et al.

Affiliated with

Also associated with

Rating

Manufacturing process of a chip package structure does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing process of a chip package structure, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing process of a chip package structure will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4096508