Manufacturing process for semiconductor wafer

Details Manufacturing process for semiconductor wafer Manufacturing process for semiconductor wafer

1999-07-07

2001-09-04

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Chemical etching

Combined with the removal of material by nonchemical means

C438S691000, C438S692000

Reexamination Certificate

active

06284658

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing process for a semiconductor wafer and more particularly, to a manufacturing process for a silicon single crystal wafer.
2. Description of the Prior Art
Conventionally, a manufacturing process for a semiconductor wafer, as shown in
FIG. 5
, has in general comprised: a slicing step E of obtaining a wafer in the shape of a thin disk by slicing a single crystal ingot which has been pulled in a single crystal pulling apparatus; a chamfering step F of chamfering peripheral edge portions of the wafer in order to prevent the sliced wafer from chipping or breaking; a lapping step L of flattening the surfaces of the chamfered wafer; a wet etching step H of removing a damaged layer remained after the chamfering and lapping steps; a mirror-polishing step K of mirror-polishing a surface of the etched wafer; and the like. While the process has sometimes been added with one or more of a various kinds of cleaning steps and value-adding steps between the above described steps, the process has fundamentally followed the above described flow.
In JP 96-66850 A (Hei 8), a technique is disclosed in which processing of a wafer is carried out in the order of a slicing step, a surface-grinding step, a chamfering step and a mirror-polishing step.
In recent years, as a planarization step, processing has also been employed in which a wafer is flattened to high accuracy by a grinding step, instead of the lapping step L, which employs a surface-grinding machine or a simultaneous double-side surface-grinding machine with the result that the ground wafer is made free of thickness variation and waviness.
As the surface grinding machine, an infeed type surface-grinding machine has generally been known in which a wafer is supported on a chuck table rotating at a high speed and a cup-shaped grinding stone (grinding wheel) is continuously fed into the wafer at a rate so as to be surface-ground.
As the simultaneous double-side surface-grinding machine, there have been known the following two machines and the like: a single wafer type double-side surface-grinding machine in which a plurality of as-cut wafers loaded on a carrier driven at a low speed in an opposed direction of that of upper and lower grinding stones driven at a high speed are sequentially supplied into between the upper grinding stone and lower grinding stone so as to be processed, and a batch type double-side grinding machine in which the upper and lower grinding stones are respectively mounted on the upper and lower tables, a plurality of wafers are inserted between the upper and lower grinding stones, being caged in wafer receive holes formed in a carrier, and both sides of each of the plurality of wafers are simultaneously ground by rotation of the lower table under pressure from the upper table (see JP 97-260314 A).
As the slicing step, a technique in which a wafer in the shape of a thin disk is obtained by slicing with a wire saw or a circular inner diameter blade has generally been adopted. Minute thickness variations and waviness in company with reciprocating movements of a wire saw are produced or inscribed on a surface of a wafer which is sliced by the wire saw. In the case of slicing with a circular inner diameter blade, levels of thickness variations and waviness are lower than those in the case of a wire saw, whereas since the blade is not suitable for slicing a larger diameter wafer, the blade is exclusively used in slicing to obtain small diameter wafers.
When a sliced wafer which has thickness variations and waviness as described above, that is having a problem in accuracy of thickness, is subjected to the chamfering step, there has arisen a problem of variations in width of a chamfered portion, as will be described below.
That is, when a wafer is chamfered along its edge portions in such a manner that a wafer
1
supported on a grinding stage
2
is pressed, while rotating at a low speed, to a grinding stone
3
rotating at a high speed as shown in
FIG. 6
, presence of thickness variations of the wafer
1
is in turn resulted in variations in width X of a chamfered portion thereof.
This will be described in a concrete manner. When, in section, an angle between a major surface of the wafer and a chamfered portion
4
is denoted as &thgr;, a chamfer width as X and a chamfer height as Y, an equation X=Y(tan &thgr;)
−1
is established. In the case of a wafer (indicated by a chain line) with a larger thickness than a standard wafer (indicated by a solid line)
1
, a chamfer width is larger to be X
1
if a load in chamfering is same. On the other hand, in the case of a wafer with a smaller thickness than the standard wafer, a chamfer width is smaller. In chamfering with the angle &thgr; of 22 degrees, which is general, a thickness variation of 10 &mgr;m entails a variation in chamfer width of about 25 &mgr;m.
When there is variations in chamfer width beyond a level, devices are hard to be fabricated in the peripheral region of a wafer to a full extent all the time, which has progressively increased a demand for improvement on a processing quality of a chamfer of wafer in recent years.
In a conventional method shown in
FIG. 5
, however, since a lapping step is included thereby, a chamfering step F is forced to be carried out prior to the lapping step L, that is, directly after a slicing step E. Hence, occurrence of variations in chamfer width has not been avoided as described above, since chamfering has to be conducted on a wafer which still has a larger thickness variation.
FIGS.
7
(A), (B) show histograms in each of which the abscissa is used for plotting the values of an accuracy in chamfer width (a chamfer width aberration) and the ordinate is assigned to a relative frequency; FIG.
7
(A) shows the values of a theoretical accuracy calculated from an accuracy of a chamfer machine and FIG.
7
(B) shows measurement results of the states of variation in chamfer width in a conventional chamfering step. Incidentally, the evaluation of an accuracy in chamfer width was carried out by measurement with an edge profiler (made by Hamamatsu Photonics Co.) which is an image processing apparatus for a projected image. The abscissa is scale-marked, for example, with “0” thereon at a chamfer width accuracy in the range of −15 &mgr;m to +15 &mgr;m. The conventional method is inferior in accuracy of chamfer width as clearly seen from the graphs.
In a method adopting a planarization step by means of a surface-grinding machine, a step different from the conventional step of
FIG. 5
can be adopted and a process flow corresponding to this has also been proposed. Any of conventional process flows has, however, been developed with attentions focused on productivity and high flatness and thus deep consideration has not been given on a quality of chamfered portion in the process flows.
SUMMARY OF THE INVENTION
The present invention has been made taking the above described problematic points into consideration and it is accordingly an object of the present invention to provide a manufacturing process for a semiconductor wafer in which a chamfering step is effected after at least one run of simultaneous double-side surface-grinding and an etching step is not employed, and which makes improvement on accuracy in a chamfered portion realized.
In order to achieve such an object, the present invention is directed to a manufacturing process of a semiconductor wafer comprising: a slicing step of obtaining a wafer in the shape of a thin disk by slicing a single crystal ingot; a surface-grinding step of flattening a surface of the wafer; a chamfering step of chamfering the peripheral edge portions of the wafer; and a mirror-polishing step of mirror-polishing the surface of the wafer, wherein a simultaneous double-side surface-grinding step of grinding both sides of the wafer simultaneously by means of a double-side grinding machine is existent prior to the chamfering step; and a secondary grinding step is performed by single-side grinding as

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