Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Making plural bipolar transistors of differing electrical...
Reexamination Certificate
1996-10-11
2003-05-20
Pham, Long (Department: 2823)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Making plural bipolar transistors of differing electrical...
C438S203000, C438S202000, C438S205000, C438S234000
Reexamination Certificate
active
06566217
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a manufacturing process thereof, and more particularly, to a semiconductor device and a manufacturing process thereof including a MOS transistor and a bipolar transistor.
2. Description of the Background
Semiconductor devices often include several types of bipolar transistors of different characteristics. For example, a semiconductor memory device requires a plurality of bipolar transistors with different-characteristics in a peripheral circuit region, which includes decoder circuit, buffer circuit, etc, formed around a semiconductor memory circuit region or a memory cell region.
FIG. 1
illustrates a characteristic of a semiconductor device which exhibits changes of current amplification (hfe) and breakdown voltage (BVces, BVceo) against process conditions (axis of abscissa). As seen in
FIG. 1
, when the breakdown voltage (BVces, BVceo) is made large as shown at a point A of the process condition, the current amplification (hfe) becomes small, while, when the current amplification (hfe) is made large as shown at a point B of the process condition, the breakdown voltage (BVces, BVceo) becomes smaller.
FIG. 2
shows the same characteristic curve as shown above for illustrating a setting of the process condition.
FIG. 2
shows a range of process conditions for satisfying both current amplification and breakdown voltage where the current amplification (hfe) exceeds the magnitude required by the design, and the breakdown voltage (BVces, BVceo) begins to exceed the value required by the design.
In a conventional method for manufacturing a semiconductor device including a plurality of bipolar transistors, the same specific kind of the current amplification (hfe) and the breakdown voltage (BVces, BVceo) are obtained for the bipolar transistors simultaneously manufactured. The impurity concentration profile for an emitter, base and collector is optimized so that the breakdown voltage can be assured, and so that the current amplification (hfe) required by the design can be obtained. This process includes an approach to change an emitter profile as shown in
FIG. 3
a
, to change a base profile as shown in
FIG. 3
b
, or to change a collector profile as shown in
FIG. 3
c
. In addition, the size of a bipolar transistor is changed to modify the characteristics depending on the usage. However, the device is becoming constantly miniaturized so that it is getting harder to satisfy both requirements for large current amplification (hfe) and high breakdown voltage.
SUMMARY OF THE INVENTION
Accordingly, the objects of the present invention are to solve the above requirements, and to provide an efficient process for manufacturing a semiconductor device which includes bipolar transistors of different characteristics, in a memory circuit region, and/or in a peripheral circuit region, which includes decoder, buffer, etc, formed around the semiconductor memory circuit region or a cell region, in response to the design requirements. The present invention is preferably applied to manufacturing concurrently a memory circuit having MOS transistors such as SRAM memory, and bipolar transistors disposed in its peripheral circuit region and/or in the memory circuit region itself.
According to an aspect of the present invention, there is provided a manufacturing process for a semiconductor device which includes a semiconductor memory circuit region containing semiconductor memories, and a peripheral circuit region disposed around the semiconductor circuit region and containing bipolar transistors. In the process, a plurality of holes are provided selectively in an insulating film of the semiconductor memory circuit region through a resist pattern; and concurrently a plurality of holes are provided selectively in an insulating film of the peripheral circuit region through a resist pattern; and bipolar transistors are formed with characteristics different from each other at the locations of the holes in the peripheral circuit region and/or in the memory circuit region.
In the manufacturing process as set forth above, the bipolar transistors with characteristics different from each other are formed by first forming emitter electrode layers in a plurality of holes in the peripheral circuit region and/or in the memory circuit region, covering the emitter electrode layer in at least one of the holes with a resist, and implanting into the emitter layer in the other of the holes impurity ions to form a different emitter.
Alternatively, as set forth, the bipolar transistors are formed by first forming emitter electrode layers in a plurality of holes in the peripheral circuit region and/or in the memory circuit region, and implanting ions in the electrode layers in a plurality of holes. Then in at least one of the holes, the emitter electrode layer is covered with a resist, and in the other of the holes impurity ions are implanted in an emitter electrode layer to form a different emitter.
In the manufacturing process as set forth above, the bases of the bipolar transistors are formed as follows. While a location of one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted in the other of the holes to form a different base.
Alternatively, while one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted in the other of the holes to form a different base.
According to another aspect of the present invention as set forth, the bipolar transistors are formed as follows. While one of a plurality of holes in the peripheral circuit region and/or in the memory circuit region is covered with a resist, plural kinds of impurity ions are implanted in the other of the holes to form a different base and a different emitter.
According to another aspect of the present manufacturing process, the bipolar transistors are formed as follows. While at least one location for forming a transistor in the peripheral circuit region is covered with a resist, additional impurity ions are implanted in the other location(s) for forming a transistor in the peripheral circuit region and/or in the memory circuit region to form a different collector region(s) by changing a concentration of impurity in the collector regions.
In another aspect of the manufacturing process as set forth above, the bipolar transistors are formed as follows. While at least one location for forming a transistor in the peripheral circuit region and/or in the memory circuit region is covered with a resist, impurity ions are implanted additionally in the other locations for forming a transistor in the peripheral circuit region to form different collector layer(s) by providing high concentration layer in the collector region(s). Alternatively, the bipolar transistors are formed by covering at least one of a plurality of holes in the peripheral circuit region with a resist, and implanting impurity ions in the other(s) of the holes to form a different collectors.
According to yet another aspect of this invention, the bipolar transistors are formed as follows. While an emitter is formed either by way of implanting ions or diffusing impurity into a base formed either by way of ion implantation or impurity diffusion in one of the holes in the peripheral circuit region and/or in the memory circuit region, an emitter is formed by implanting ions in a well of one conductivity type surrounded by another well of another conductivity type in the other of the holes in the peripheral circuit region and/or in the memory circuit region.
Further, according to the present invention, there is provided a manufacturing process for a semiconductor device which includes a semiconductor memory circuit region containing semiconductor memories, and a peripheral circuit region disposed around the semiconductor memory circuit region, and containing bipolar transistors, in which a plurality of holes are provided
Brairton S A
Mitsubishi Denki & Kabushiki Kaisha
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Pham Long
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