Manufacturing process for an integrated circuit comprising doubl

Details Manufacturing process for an integrated circuit comprising doubl Manufacturing process for an integrated circuit comprising doubl

1988-12-14

1991-03-05

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 43, 437 49, 437 52, 437203, H01L 21425, H01L 2176, H01L 2178

Patent

active

049977776

ABSTRACT:
A process for manufacturing integrated circuits comprising insulated gate MOS transistors and double gate memory components, comprises the following steps: forming on the areas where the memory components will be formed a first insulating layer (2) and a first gate level (4); forming on the transistor areas and the memory areas a second insulating layer (5), a second gate level (6) and a first photoresist layer (7); etching the first photoresist layer and the second gate level according to chosen configurations; coating the transistor areas with a second photoresist layer (20). This process further comprises the following steps: selectively etching the second photoresist layer at the center of the places where the transistor drains and sources are to be formed; etching the apparent oxide areas and then the apparent gate and substrate areas; removing the second photoresist layer; and carrying out an ionic implantation of the drains and sources.

REFERENCES:
patent: 4635347 (1987-01-01), Lien et al.
patent: 4755479 (1988-07-01), Miura
patent: 4766088 (1988-08-01), Kono et al.
D. L. Bergeron et al., "Aluminum Gate Self-Aligned FET", IBM Technical Disclosure Bulletin, vol. 21, No. 8, Jan. 1979.

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