Manufacturing process for a semiconductor device using bias ECRC

Details Manufacturing process for a semiconductor device using bias ECRC Manufacturing process for a semiconductor device using bias ECRC

1990-10-25

1993-09-07

Hearn, Brian E.

Fishing, trapping, and vermin destroying

437 63, 437 64, 148DIG50, H01L 2100, H01L 2102, H01L 2176

Patent

active

052428532

ABSTRACT:
A semiconductor device manufacturing process and a bias ECRCVD apparatus for the process. The semiconductor device manufacturing process comprises the steps of forming trenches in the surface of a substrate, forming an insulating film by bias ECRCVD over the surface of the substrate, etching the insulating film by lateral leveling etching so as to expand the width of grooves formed in portions of the insulating film which are formed in regions other than those corresponding to the trenches, masking the portions of the insulating film which fill the trenches and removing the portions of the insulating film formed in the regions other than those corresponding to the trenches. An etching stop layer is formed over the surface of the substrate before forming the trenches and the insulating film, and the etching stop layer is removed by etching after removing the portions of the insulating film which are formed in the regions other than those corresponding to the trenches by etching with the portions of the insulating film which fill up the trenches masked. The surfaces of the portions of the insulating film which fill up the trenches are finished so as to be flush with the surface of the substrate. Desirably, the etching stop layer is annealed so as to make the grains of the surface of the etching stop layer smooth so as to enable the complete removal of the portions of the insulating film formed in the regions other than those corresponding to the trenches.

REFERENCES:
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patent: 4274909 (1981-06-01), Venkataraman et al.
patent: 4554728 (1985-11-01), Shepard
patent: 4666556 (1987-05-01), Fulton et al.
patent: 4851366 (1989-07-01), Blanchard
Albas, S., Recessed Oxide Isolation Process, IBM Tech. Disclosure Bull., vol. 20, No. 1, Jun. 1977, pp. 144-145.

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