Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Making plural bipolar transistors of differing electrical...
Reissue Patent
1995-02-06
2004-05-04
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Making plural bipolar transistors of differing electrical...
C438S375000, C438S419000
Reissue Patent
active
RE038510
ABSTRACT:
This invention concerns a manufacturing process for a monolithic semiconductor device comprising at least one transistor of an integrated control circuit and one power transistor integrated on the same chip.
The association of vertical flow high voltage power transistors and an integrated control circuit on the same chip results in an extremely compact and efficient device with advantages over those using separate components.
In said device the distance between the lower margin of the horizontal insulating region and the underlying substrate cannot fall below a certain limit d, the value of which depends on the operating voltage of the device. The current rating of the power stage, on the other hand, will rise in proportion to the decrease in thickness of the collector and therefore reaches the maximum permissible value when the thickness reaches the minimum level d permitted by the operating voltage. It is therefore advantageous for the device to be made in such a way that the depth of the junction of the horizontal insulating region and that of the base of the power transistor coincide.
An attempt to solve the aforesaid problem is represented by the procedure described in the U.S. Pat. No. 4,239,558 which, however, involves very heavy doping in the base and emitter regions of the integrated control circuit transistor, resulting in the lowering of the relative break-down values of the junctions of the integrated control circuit transistors and between the collectors of the latter and the horizontal insulating region. The scope of the invention is to provide a manufacturing process for a semiconductor device of the above-described type, by means of which it is possible to maximize the current rating of the power stage and the operating voltage of the integrated control circuit. For this purpose, the process comprises the following phases:
the epitaxial growth on a semiconductor substrate (
11
) of a first type of conductivity, of a semiconductor layer (
22
) which is also of the aforesaid first type of conductivity;
the simultaneous formation, by diffusion of doping agent within the surface of the layer (
22
), of a first semiconductor region (
23
) and a second semiconductor region (
24
) of a second type of conductivity, said first region (
23
) constituting the base region of the power transistor, said second region (
24
) constituting the horizontal insulating region of the integrated control circuit with respect to the power transistor;
the simultaneous formation, by diffusion within the surface of the aforesaid regions (
23
) and (
24
), of two regions (
25
) and (
26
), respectively, of the first type of conductivity, constituting, respectively, the emitter region of the power transistor and the buried layer of the collector region of the integrated control circuit transistor;
the formation, by further subsequent superficial diffusions, of the base (
15
) and the emitter (
16
) of the aforesaid transistor of the integrated control circuit;
the formation, by simultaneous diffusion, of connecting regions (
21
) and (
19
), at the surface (
12
) of the horizontal insulating region (
24
) and base region (
23
) of the power transistor, respectively;
the formation, by simultaneous diffusion, of enrichment regions (
13
) and (
14
) for the emitter (
25
) of the power transistor and the buried layer (
26
) of the integrated control circuit transistor, respectively;
and is characterized by the fact that the formation of the regions (
21
), (
19
), (
13
) and (
14
) of the base (
15
) and of the emitter (
16
) of the transistor of the integrated control circuit is preceded by the epitaxial growth of a semiconductor layer (
17
) of the first type of conductivity.
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patent: 3956035 (1976-05-01), Herrmann
patent: 4032372 (1977-06-01), Vora
patent: 4054899 (1977-10-01), Stehlin et al.
patent: 4404048 (1983-09-01), Vogelsang
patent: 4483738 (1984-11-01), Blossfeld
patent: 4641171 (1987-02-01), Bertotti et al.
patent: 4641172 (1987-02-01), Iwatani
patent: 4721684 (1988-01-01), Musumeci
patent: 4780430 (1988-10-01), Musumeci et al.
patent: 4826780 (1989-05-01), Takemoto et al.
patent: 2543364 (1984-09-01), None
Musumeci Salvatore
Zambrano Raffaele
Chaudhari Chandra
Jorgenson Lisa K.
STMicroelectronics Srl
Szuwaiski Andre
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