Manufacturing process for a chip package structure

Details Manufacturing process for a chip package structure Manufacturing process for a chip package structure

2008-11-13

2010-12-14

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C257SE21499, C438S106000, C438S126000, C438S617000

Reexamination Certificate

active

07851262

ABSTRACT:
A manufacturing process for a chip package structure is provided. First, a patterned conductive layer and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires, wherein the chips and the bonding wires are at the same side of the patterned conductive layer. A molding compound is formed to encapsulate the patterned conductive layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

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patent: 1501488 (2004-06-01), None
U.S. Office Action of U.S. Appl. No. 11/326,2006, dated Dec. 5, 2008.

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