Manufacturing process for a chip package structure

Details Manufacturing process for a chip package structure Manufacturing process for a chip package structure

2008-11-13

2010-12-14

Sarkar, Asok K (Department: 2891)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Insulative housing or support

C257S686000, C257SE21499, C438S108000, C438S617000

Reexamination Certificate

active

07851270

ABSTRACT:
A manufacturing process for a chip package structure is provided. First, a patterned conductive layer having a plurality of first openings and a patterned solder resist layer on the patterned conductive layer are provided. A plurality of chips are bonded onto the patterned conductive layer such that the chips and the patterned solder resist layer are disposed at two opposite surfaces of the patterned conductive layer. The chips are electrically connected to the patterned conductive layer by a plurality of bonding wires passing through the first openings of the patterned conductive layer. At least one molding compound is formed to encapsulate the patterned conductive layer, the patterned solder resist layer, the chips and the bonding wires. Then, the molding compound, the patterned conductive layer and the patterned solder resist layer are separated.

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patent: 7091581 (2006-08-01), McLellan et al.
patent: 2002/0039808 (2002-04-01), Fukutomi et al.
patent: 2006/0223234 (2006-10-01), Terayama et al.
patent: 1501488 (2004-06-01), None
U.S. Office Action of U.S. Appl. No. 11/326,749, dated Dec. 5, 2008.

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