Semiconductor device manufacturing: process – Making passive device – Stacked capacitor
Patent
1998-10-14
2000-07-18
Arroyo, Teresa M.
Semiconductor device manufacturing: process
Making passive device
Stacked capacitor
438253, 438254, 438255, 438396, 438398, 438964, H01L 218242
Patent
active
060906804
ABSTRACT:
A method for manufacturing a capacitor, applied to a memory unit including a substrate forming thereon a dielectric layer forming thereon a first conducting layer, includes the steps of a) forming a sacrificial layer over the first conducting layer, b) partially removing the sacrificial layer, the first conducting layer, and the dielectric layer to form a contact window, c) forming a second conducting layer over the sacrificial layer and in the contact window, d) partially removing the second conducting layer and the sacrificial layer to expose a portion of the sacrificial layer and retain a portion of the second conducting layer, and e) forming a third conducting layer alongside the portions of the second conducting layer and the sacrificial layer, and removing the portion of the sacrificial layer to expose the first conducting layer, wherein the first conducting layer, the portion of the second conducting layer, and the third conducting layer construct a capacitor plate with a generally crosssectionally modified T-shaped structure.
REFERENCES:
patent: 5137842 (1992-08-01), Chan et al.
patent: 5432116 (1995-07-01), Keum et al.
patent: 5721168 (1998-02-01), Wu
patent: 5759895 (1998-06-01), Tseng
Arroyo Teresa M.
Mosel Vitelic Inc.
Thomas Toniae M.
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