Manufacturing methods of semiconductor devices and a solid...

Active solid-state devices (e.g. – transistors – solid-state diode – Transmission line lead

Reexamination Certificate

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C257S750000, C257S662000, C438S453000, C438S720000

Reexamination Certificate

active

07087983

ABSTRACT:
A manufacturing method of manufacturing a semiconductor device having a plurality of wiring layers. The method includes the steps of forming a wiring by a first wiring layer as a pattern by dividing a desired pattern into a plurality of patterns, connecting the divided patterns, and exposing them, wherein a position of the connection is formed in parallel with the wiring which is formed by the first wiring layer, and forming a wiring by a second wiring layer having an area which intersects the connecting position by a batch processing of exposure.

REFERENCES:
patent: 5561317 (1996-10-01), Momma et al.
patent: 5731131 (1998-03-01), Momma et al.
patent: 6197452 (2001-03-01), Matumoto
patent: 6204912 (2001-03-01), Tsuchiya et al.
patent: 6518180 (2003-02-01), Fukuda
patent: 4-326507 (1992-11-01), None
patent: 5-127186 (1993-05-01), None

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