Manufacturing method of silicon on insulator wafer

Details Manufacturing method of silicon on insulator wafer Manufacturing method of silicon on insulator wafer

2005-08-26

2009-10-13

Coleman, W. David (Department: 2813)

Semiconductor device manufacturing: process

Bonding of plural semiconductor substrates

Subsequent separation into plural bodies

C257SE21568

Reexamination Certificate

active

07601614

ABSTRACT:
A process for manufacturing a silicon on insulator (SOI) substrate is described. The process includes forming a buried oxidation layer in a first wafer and forming an oxidation layer on the first wafer. A buried hydrogen layer is formed in the first wafer deeper than the buried oxidation layer. A second wafer is bonded onto the first oxidation layer. The first wafer is removed below the buried hydrogen layer to expose the first wafer between the buried oxidation layer and the buried hydrogen layer. The exposed first wafer and the buried oxidation layer are sequentially removed to expose the first wafer between the buried oxidation layer and the first oxidation layer. Finally, a predetermined thickness of the first wafer exposed in the previous step is removed. Accordingly, a highly uniform and ultra thin SOI substrate is formed without employing a CMP process.

REFERENCES:
patent: 6211041 (2001-04-01), Ogura
patent: 6251754 (2001-06-01), Ohshima et al.
patent: 6306730 (2001-10-01), Mitani et al.
patent: 6368938 (2002-04-01), Usenko
patent: 6423614 (2002-07-01), Doyle
patent: 6613678 (2003-09-01), Sakaguchi et al.
patent: 6661065 (2003-12-01), Kunikiyo
patent: 6770507 (2004-08-01), Abe et al.
patent: 7018484 (2006-03-01), Atanackovic
patent: 7084046 (2006-08-01), Mitani et al.
patent: 7217584 (2007-05-01), Yue et al.
patent: 7217636 (2007-05-01), Atanackovic
patent: 7276430 (2007-10-01), Kwon
patent: 7387946 (2008-06-01), Dao
patent: 2002/0182827 (2002-12-01), Abe et al.
patent: 2003/0207545 (2003-11-01), Yasukawa
patent: 2005/0029592 (2005-02-01), Campbell et al.
patent: 2005/0042841 (2005-02-01), Boyd et al.
patent: 2005/0048703 (2005-03-01), Dennard et al.
patent: 2005/0282318 (2005-12-01), Dao
patent: 2006/0068565 (2006-03-01), Droes et al.
patent: 2006/0128075 (2006-06-01), Kwon
patent: 2006/0141786 (2006-06-01), Boezen et al.
patent: 2006/0160327 (2006-07-01), Barna
patent: 2006/0228492 (2006-10-01), Aoki et al.
patent: 2007/0004169 (2007-01-01), Endo et al.
patent: 2007/0069335 (2007-03-01), Endo et al.
patent: 04-115511 (1992-04-01), None
patent: 07-263538 (1995-10-01), None
patent: 11-121377 (1999-04-01), None
patent: 1020020002998 (2002-01-01), None
Quirk M. Semiconductor Manufacturing Technology, Prentice Hall, 2001, pp. 500-501.
‘Dose-energy match for the formation of high-integrity buried oxide layers in low-dose separation-by-implantation-of-oxygen materials’ Chen et al., Applied Physics Letters, vol. 80, No. 5, Feb. 4, 2002, pp. 880-882.
‘Formation of Si islands in the buried oxide layers of ultra-thin SIMOX structures implanted at 65 keV’ Jiao et al., Materials Science and Engineering B72 (2000) 150-155.

Affiliated with

Also associated with

Rating

Manufacturing method of silicon on insulator wafer does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Manufacturing method of silicon on insulator wafer, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method of silicon on insulator wafer will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4064656