Manufacturing method of shallow trench isolation

Details Manufacturing method of shallow trench isolation Manufacturing method of shallow trench isolation

2005-03-08

2005-03-08

Zarabian, Amir (Department: 2822)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S435000, C438S778000, C438S786000

Reexamination Certificate

active

06864150

ABSTRACT:
The present invention disclosed a manufacturing method of shallow trench isolation (STI). By making use of depositing two layer of SiON with specific thickness and different extinction coefficient (k) as the ARC, comprising: (a) Depositing pad oxide/silicon nitride on a substrate as a hard mask for etching; (b) Depositing a layer of high extinction coefficient SiON on said silicon nitride, then depositing a layer of low extinction coefficient SiON as the ARC; (c) Exposing by using a STI mask and developing to form an etching mask of said STI; (d) Etching said SiON, silicon nitride, pad oxide and said substrate to form a shallow trench; (e) Growing an oxide layer on the side-wall and the bottom of said shallow trench to remove damage and decrease leakage; (f) Depositing an oxide layer on said shallow trench and said silicon nitride to fill said shallow trench; (g) planarizing by CMP.

REFERENCES:
patent: 6383874 (2002-05-01), Sun et al.
patent: 6624068 (2003-09-01), Thakar et al.
patent: 6713831 (2004-03-01), Sadoughi et al.
patent: 6777336 (2004-08-01), Lin et al.
patent: 20020009845 (2002-01-01), Bhakta et al.

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