Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2000-12-29
2004-10-26
Goudreau, George A. (Department: 1763)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S725000, C438S751000, C438S749000, C438S734000, C430S005000
Reexamination Certificate
active
06809037
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor integrated circuit including simultaneous formation of a via hole reaching a metal wiring and a concave groove in an interlayer film, and a semiconductor integrated circuit manufactured with the manufacturing method.
2. Description of the Relate Art
In recent years, higher performance and finer size are required for semiconductor integrated circuits, and various manufacturing methods and materials for use are under study. Conventionally, polysilicon and aluminum have often been used for wirings in the semiconductor integrated circuits. However, materials with lower resistance are needed to realize higher performance and finer size of the semiconductor integrated circuits.
To address such a need, the use of copper has been proposed to form fine wirings in a semiconductor integrated circuit. However, copper has properties which make patterning with etching difficult, and has low corrosion resistance. Thus, a dual damascene method has been developed as a method of manufacturing a semiconductor integrated circuit in which metal wirings made of copper are formed within and on a surface of an interlayer film and the metal wirings are connected to each other with a contact made of copper.
A prior art of the method of manufacturing a semiconductor integrated circuit with the dual damascene method is hereinafter described with reference to
FIG. 1A
to FIG.
4
C. The drawings of
FIG. 1A
to
FIG. 4C
are front section views sequentially showing manufacturing steps of a semiconductor integrated circuit.
First, semiconductor integrated circuit
100
to be manufactured in this case is described. As shown in
FIG. 4C
, semiconductor integrated circuit
100
comprises lower interlayer film
101
made from SiO
2
and upper interlayer film
102
. Upper interlayer film
102
is disposed on stopper film
115
layered on the surface of the lower interlayer film
101
. Lower metal wiring
103
made of copper is embedded in an upper portion of lower interlayer film
101
. Upper metal wiring
104
made of copper is also embedded in an upper portion of upper interlayer film
102
, and connecting wiring
105
formed integrally with upper metal wiring
104
is connected to lower metal wiring
103
.
Lower metal wiring
103
and upper metal wiring
104
extend, for example, in a direction passing through the drawing (hereinafter referred to as “front-to-back direction”). Connecting wiring
105
is formed to have the front-to-back length identical to the left-to-right width, for example. Connecting wiring
105
which does not extend in the front-to-back direction connects lower metal wiring
103
to upper metal wiring
104
at one point.
As a typical method of manufacturing semiconductor integrated circuit
100
configured as described above, as shown in
FIG. 1A
, lower interlayer film
101
made from SiO
2
with a predetermined thickness is formed on a surface of silicon substrate
100
, and a photoresist (not shown) is applied on the surface thereof and then patterned to form a resist mask (not shown). Lower interlayer film
101
is dry etched through an opening in the resist mask, thereby forming concave
111
with a predetermined depth on the surface of lower interlayer film
101
as shown in FIG.
1
B.
After concave
111
is completed, the resist mask is removed with plasma processing and organic removal in an atmosphere of O
2
. Then, as shown in
FIG. 1C
, tantalum film
112
and copper film
113
are sequentially formed with sputtering on the surface of exposed lower interlayer film
101
.
Next, as shown in
FIG. 1D
, plating film
114
made of copper is formed on the surface of copper film
113
to fill concave
111
. As shown in
FIG. 1E
, plating film
114
, copper film
113
, and tantalum film
112
are polished flatly with CMP (Chemical Mechanical Polishing) until the surface of lower interlayer film
101
is exposed.
Next, as shown in
FIG. 2A
, stopper film
115
made from SiN is grown to have a thickness of 500 [Å], for example, on the surface of the flatly polished surface with a plasma CVD (Chemical Vapor Deposition) process. Then, upper interlayer film
102
made from SiO
2
is grown to have a thickness of 12000 [Å], for example, on the surface of stopper film
115
with the plasma CVD process.
Resist mask
116
with an opening above upper metal wiring
103
is then formed on the surface of upper interlayer film
102
, and upper interlayer film
102
is etched through the opening in resist mask
116
, thereby forming via hole
117
extending from the surface of upper interlayer film
102
to the surface of stopper film
115
at the position opposite to lower metal wiring
103
.
Resist mask
116
is removed after via hole
117
is formed. As shown in
FIG. 2C
, ARC (Anti Reflective Coating) film
118
serving as an organic film is formed to have a thickness of 2000 [Å] on the surface of upper interlayer film
102
, and the material of ARC film
118
is filled in via hole
117
.
Resist mask
119
with an opening wider than via hole
117
is formed to have a thickness of 8000 [Å], for example, on the surface of ARC film
118
. Then, in an atmosphere where an etching gas formed by mixing “C
4
F
8
” and “O
2
,” and an inert gas including “Ar” are maintained at a pressure of approximately 30 [mTorr], ARC film
118
is plasma etched through the opening in resist mask
119
as shown in FIG.
2
D. The mixing ratio of “C
4
F
8
”:“O
2
”:“Ar” is “20:10:200”, for example.
After ARC film
118
is plasma etched, the etching gas is changed to “C
4
F
8
” only, and as shown in
FIG. 3A
, ARC film
118
and upper interlayer film
102
are simultaneously plasma etched through the opening in resist mask
119
to form concave groove
120
which is wider than via hole
117
. The depth of concave groove
120
is 4000 [Å] which does not reach stopper film
115
.
At this point, since the etching rate of the plasma etching of upper interlayer film
102
and ARC film
118
with the etching gas including “C
4
F
8
” is approximately “4000 Å/min,” the depth of concave groove
120
can be adjusted to 4000 [Å] by performing the etching for 1 minute.
Next, by means of plasma processing with “O
2
” and removal processing with an amine organic remover, resist mask
119
and ARC film
118
are removed as shown in
FIG. 3B
to expose stopper film
115
at the bottom of via hole
117
. It should be noted that while lower metal wiring
103
made of copper has low corrosion resistance, it is not subjected to corrosion since lower metal wiring
103
is shielded from surrounding environments by stopper film
115
when resist mask
119
and ARC film
118
are removed as described above.
Subsequently, in an atmosphere of an etching gas formed by mixing “CHF
3
” and “O
2
,” and an inert gas including “Ar,” stopper film
115
exposed at the bottom of via hole
117
is plasma etched with upper interlayer film
102
used as a mask to expose lower metal wiring
103
at the bottom of via hole
117
as shown in FIG.
3
C. The mixing ratio of “CHF
3
”:“O
2
”:“Ar” is also “20:10:200”, for example.
In this state, the exposed surfaces of upper interlayer film
102
and lower metal wiring
103
are cleaned with an amine organic remover, and as shown in
FIG. 4A
, tantalum nitride film
121
and copper film
122
are sequentially formed on the cleaned surfaces with sputtering. Thus, tantalum nitride film
121
and copper film
122
are formed to cover the upper surface of upper interlayer film
102
and the inner surfaces of concave groove
120
and via hole
117
.
Then, as shown in
FIG. 4B
, plating film
123
made of copper is formed on the surface of copper film
122
. At this point, the material of plating film
123
is filled in concave groove
120
and via hole
117
.
Plating film
123
, copper film
122
, and tantalum nitride film
121
are flatly polished with the CMP until the surface of upper
Goudreau George A.
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
LandOfFree
MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and MANUFACTURING METHOD OF SEMICONDUCTOR INTEGRATED CIRCUIT... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3324918