Fishing – trapping – and vermin destroying
Patent
1995-06-07
1996-03-19
Hearn, Brian E.
Fishing, trapping, and vermin destroying
437201, 437245, 437246, 437919, 216 6, 216 62, 216 72, 216 75, 1566521, 1566561, 148DIG14, H01L 2170
Patent
active
055003869
ABSTRACT:
A method of manufacturing a semiconductor device, where on top of a substrate having already-completed circuit elements and wiring, etc., an insulation underlayer a, Pt layer for a bottom electrode, a dielectric film and a Pt layer for a top electrode are shaped.
A top electrode, capacitance insulation film and bottom electrode are formed by etching the Pt layer for the top electrode or the Pt layer for the bottom electrode using an etching gas contained an S component while composing a Pt and S compound. Alternatively the Pt and S compound can be composed first, and then the compound can be etched.
REFERENCES:
patent: 3923568 (1975-12-01), Bersin
patent: 5122477 (1992-06-01), Wolters et al.
patent: 5439840 (1995-08-01), Jones, Jr. et al.
patent: 5440173 (1995-08-01), Evans, Jr. et al.
Matsumoto Shoji
Nakagawa Satoshi
Nikou Hideo
Dang Trung
Hearn Brian E.
Matsushita Electronics Corporation
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