Semiconductor device manufacturing: process – Having magnetic or ferroelectric component
Reexamination Certificate
2001-04-19
2002-12-31
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Having magnetic or ferroelectric component
C438S253000
Reexamination Certificate
active
06500675
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices having capacitive elements and manufacturing methods thereof. More particularly, the present invention relates to a semiconductor device having a plurality of metal interconnection layers on a semiconductor substrate and having a capacitive element in an opening of an insulating layer between upper and lower metal interconnection layers as well as a manufacturing method thereof.
2. Description of the Background Art
FIG. 16
is a cross sectional view schematically showing a structure of a conventional semiconductor device having a capacitive element. A capacitive element C has a lower electrode
109
, a dielectric layer for capacitive element
110
, and an upper electrode
112
. Lower electrode
109
is formed on a surface of a semiconductor substrate
101
, which is isolated by a trench isolation
102
and formed when a gate electrode
105
of a transistor T is formed. Lower electrode
109
has a stack of a polysilicon layer
109
a
doped with impurities and a high melting point metal film
109
b
of, for example, W (tungsten), Ti (titanium), Co (cobalt), Ni (nickel) or Mo (molybdenum), or a silicide
109
b
thereof. Upper electrode
112
is formed on lower electrode
109
with dielectric layer for capacitive element
110
interposed. Upper electrode
112
is a polysilicon or amorphous silicon doped with impurities such as P (phosphorus) or As (arsenic), or a compound of a high melting point metal film such as TiN (titanium nitride). Dielectric layer for capacitive element
110
is, for example, a high dielectric film such as a silicon oxide film, silicon nitride film or tantalum oxide film formed by CVD (Chemical Vapor Deposition).
An interlayer insulating layer
107
is formed to cover capacitive element C. Each of lower electrode
109
and upper electrode
112
is electrically connected to a metal interconnection
113
through a metal plug
108
filling in a contact hole
107
a.
Metal interconnection
113
applies a potential to each of lower electrode
109
and upper electrode
112
, so that electric charges are accumulated between the electrodes.
Note that transistor T has a pair of source/drain regions
103
, a gate insulating layer
104
, and a gate electrode layer
105
. The pair of source/drain regions
103
are separated on the surface of semiconductor substrate
101
. Gate electrode layer
105
is formed on the region between the pair of source/drain regions
103
through gate insulating layer
104
. An insulating layer
106
is formed on gate electrode layer
105
. Each of the pair of source/drain regions
103
is electrically connected to metal interconnection
113
through metal plug
108
in contact hole
107
a.
In the semiconductor device having a conventional capacitive element, the surface of interlayer insulating layer
107
covering capacitive element C and transistor T is planarized by CMP (Chemical Mechanical Polishing). The planarization is performed to reduce steps at the surface of interlayer insulating layer
107
, so as to facilitate pattern formation at the upper layer by photolithography for greater dimensional accuracy.
When the planarization is performed by CMP, however, the upper surface of interlayer insulating layer
107
is planarized almost completely, whereby a thickness h
1
of films on gate electrode
105
becomes smaller than a thickness h
3
of a film on source/drain region
103
by a thickness of gate electrode
105
. Likewise, a thickness h
2
of a film on upper electrode
112
becomes smaller than thickness h
1
of films on gate electrode
105
by the thicknesses of dielectric layer for capacitive element
110
and upper electrode
112
.
Usually, there is a variation in thickness of films removed at the time of planarization by CMP. Thus, thickness h
2
must be sufficiently large to prevent exposure of upper electrode
112
from interlayer insulating layer
107
during planarization. However, as thickness h
2
increases, thickness h
3
of the film on source/drain region
107
inevitably increases. The increase in thickness h
3
results in greater aspect ratio of contact hole
107
a
(a ratio of depth to diameter of contact hole
107
a
) reaching source/drain region
103
. As a result, it becomes difficult to stably form, by dry etching, contact hole
107
a
with sufficient dimensional accuracy. In some cases, the etching stops en route, preventing proper formation of contact hole
107
a.
A technique for solving the aforementioned problem is disclosed in Japanese Patent Laying-Open No. 11-274428.
FIG. 17
is a cross-sectional view schematically showing a structure of a semiconductor device having a capacitive element disclosed in the aforementioned laid-open application No. 11-274428. Referring to
FIG. 17
, capacitive element C has a lower electrode
209
, a dielectric layer for capacitive element
210
, and an upper electrode
212
A. Lower electrode
209
is formed on a silicon oxide film
207
[
209
] on a silicon substrate
201
, having a polysilicon film
209
a
and a titanium silicide film
209
b.
Upper electrode
212
A is formed to fill in a hole
211
a
opened in an interlayer insulating layer
211
. Upper electrode
212
A is electrically connected to an aluminum interconnection
213
A deposited on interlayer insulating layer
211
.
Now, a method of manufacturing the semiconductor device having the capacitive element will be described.
FIGS. 18
to
23
are schematic cross sectional views sequentially showing the method of manufacturing the semiconductor device having the capacitive element shown in FIG.
17
. Referring to
FIG. 18
, after silicon oxide film
207
is formed on silicon substrate
201
, a lower electrode
209
having polysilicon film
209
a
and titanium silicide film
209
b
is formed.
Referring to
FIG. 19
, interlayer insulating layer
211
is formed to cover lower electrode
209
. An opening
211
a
reaching lower electrode
209
a
is opened in interlayer insulating layer
211
. A silicon nitride film
210
, later to be a dielectric layer for capacitive element, is formed over the entire surface to cover the inner surface of opening
211
a.
Referring to
FIG. 20
, a contact hole
211
b
reaching lower electrode
209
is formed in interlayer insulating layer
211
and silicon nitride film
210
.
Referring to
FIG. 21
, a tungsten film
212
is formed over the entire surface to fill in hole
211
a
and contact hole
211
b.
Thereafter, tungsten film
212
is polished by CMP.
Referring to
FIG. 22
, the upper surface of silicon nitride film
210
is exposed by CMP, so that upper electrode
211
A and a plug conductive layer
212
B of tungsten are formed.
Referring to
FIG. 23
, any unwanted portion of silicon nitride film
210
, exposed from the surface, is removed by dry etching.
Thereafter, the aluminum interconnection layer is formed to complete a semiconductor device having capacitive element C as shown in FIG.
17
.
In the structure shown in
FIG. 17
, upper electrode
212
A for capacitive element C is formed as a plug layer filling in hole
211
A. Thus, upper electrode
212
A can be electrically connected to aluminum interconnection layer
213
B directly at the upper surface of interlayer insulating layer
211
. This eliminates the need for a contact hole connecting upper electrode
212
A and aluminum interconnection
213
B, so that the thickness of interlayer insulating layer
211
is restrained. Thus, the problem as described in conjunction with the structure of
FIG. 16
, associated with greater thickness h
3
of the film on source/drain region
103
, can be alleviated.
However, the structure shown in
FIG. 17
still suffers from problems associated with a complicated manufacturing process or insufficient capacity of the capacitive element when diffusion of metal atoms from a lower electrode is considered. In the following, the problems will be described in detail.
(1) Increased number of manufacturing steps
In the structure shown in
FIG. 17
, for example, if copper (Cu) is used
Izumitani Junko
Sunada Shigeki
Takata Yoshifumi
McDermott & Will & Emery
Tsai Jey
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