Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2001-12-18
2003-06-24
Picardat, Kevin M. (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S427000, C438S690000, C438S692000
Reexamination Certificate
active
06583027
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a method of manufacturing and a method of designing a semiconductor device which provide chemical mechanical polishing capable to attain an excellent planarity for the polished surface, and more particularly to a method of fabricating a buried trench structure.
For the purpose of achieving a higher integration in a semiconductor device, a conventional method such as the LOCOS (LOCal Oxidation of Silicon) method is often applied to the formation of an element isolation region. However, there are known instances where such a method cannot achieve satisfactory electrical isolation between elements. As a method of fabricating an element isolation region to replace the LOCOS method, the Shallow Trench Isolation method (referred to as the STI hereinafter) has been, thereupon, put into practical use.
In the STI, a trench is formed in a semiconductor substrate and then an insulating material film is grown so as to fill up the trench. Subsequently, by the chemical mechanical polishing (referred to as the CMP hereinafter) method, the insulating material film present in the area other than the inside of the trench is removed and thereby a buried trench structure filled up with the insulating material is fabricated.
FIG. 6
shows an example of a layout in which a memory cell region
75
which is provided with a plurality of memory cell formation regions
77
partitioned by a plurality of trenches and an adjacent region
70
which is provided with adjacent element formation regions
74
. partitioned by an element isolation region
71
are disposed. Further,
FIG. 7
illustrates a method of manufacturing a semiconductor device having such a layout as shown in FIG.
6
. First, s shown in FIG.
7
(
a
), a trench
79
with a large width is formed in the element isolation region
71
. Next, as shown in FIG.
7
(
b
), a film for polishing
78
is grown from an isolating material to fill up the trench
79
. The film for polishing present in the area other than the inside of the trench
79
is then removed by the CMP, and thereby an element isolation region made of a buried trench structure with a large width, being filled up with an insulating material, is formed.
However, with the layout shown in
FIG. 6
, when the growth of the film for polishing
78
is completed and the CMP starts, although, in the memory cell region
75
, the film for polishing comes into contact with a polishing pad with a large area, in the adjacent region
70
, a contact area between the film for polishing and the polishing pad is small. Since the polishing rate becomes low for the section where a large area of the film for polishing is in contact with the polishing pad, and high for the section where only a small area thereof is in contact therewith, the difference between the polishing rates may cause a considerable deviation in polishing. Because of this, after the completion of the CMP, dishing, erosion and the like may be left on the substrate surface, as shown in FIG.
7
(
c
), unable to attain satisfactory planarity. Dishing, as used herein, indicates a state that the insulating material in the trench becomes polished so that the center of the insulating material within the trench falls in. On the other hand, erosion, as used herein, indicates a state that the polishing over the entire region proceeds excessively and the surface of the entire region falls in.
To avoid these adverse effects, various investigations have been made so far and, for example, formation of a dummy pattern in the element formation region has been proposed.
For instance, in Japanese Patent Application Laid-open No. 107028/1997, it is disclosed that dishing can be prevented by setting a layout such as a dummy pattern that is identical to a pattern formed in a cell site is inserted into a field region with a wide trench, within the limit of not affecting the transistor performance, and making the height of the major part of the dummy pattern equal to that in the cell site immediately before the CMP. However, the method described in this publication is not very practical, because the pattern in the cell site is minutely formed and, thus, the insertion of a dummy pattern that is identical to that pattern into the field region greatly increases the amount of data in reticle fabrication.
Further, in Japanese Patent Application Laid-open No. 107028/1997, there is described a case in which a dummy pattern is not identical to a pattern in a cell region but comprising a line/space pattern that can diminish a difference in level between the cell site and dummy pattern site from the viewpoint of the CMP. Nevertheless, therein, it is not specifically described how to set a dummy pattern if the dummy pattern is not identical to the pattern in the cell region.
Further, in Japanese Patent Application Laid-open No. 92921/1998, it is disclosed that, by forming a pattern of dummy structure in a second region, a polishing rate of the second region is adjusted to become almost the same as a polishing rate of a first region, whereby dishing is prevented from occurring. In particular, an occupation density is defined as a ratio of an area occupied by the dummy structure in the first region to a total surface area of the first region therein. Further, it is described that the occupation density of the dummy structure should be adjusted to coincide well with the density of the structure which is present in the second region and preferably set to be 5-40%.
In effect, it is proposed, in this publication, that, as shown in
FIG. 8
, when a plurality of dummy patterns
83
partitioned by a plurality of trenches
82
are formed in an element isolation region
81
, dummy patterns are designed on the basis of a ratio (referred to as an occupation density of dummy patterns hereinafter) of a total sum of top surface areas for a plurality of dummy patterns
83
to a horizontally projected area of an adjacent region
80
. Presumably, such a designing method can, while preventing the amount of data from increasing unduly by setting the occupation density of dummy patterns within an appropriate range, fabricate dummy patterns
83
having an occupation density different from the one for a memory cell region
85
, and thereby suppress dishing and erosion well.
However, there are instances where the substrate surface cannot attain satisfactory planarity even though dummy patterns having a prescribed occupation density are formed in the element isolation region.
Such a state is described, with reference to FIG.
9
. First, as shown in FIG.
9
(
a
), dummy patterns
83
partitioned by a plurality of first trenches
82
are fabricated in an element isolation region
81
within an adjacent region
80
. Hereat, taking occupation densities of respective patterns for memory cell regions
87
and adjacent element formation regions
84
into consideration, an occupation density of dummy patterns
83
is made to have a prescribed value within the limit the resulting increase in amount of data is well controllable. Further, the occupation density of dummy patterns
83
can differ from the occupation density of memory cell formation regions
87
, if required.
Next, as shown in FIG.
9
(
b
), a film for polishing
88
is formed from an insulating material to fill up first trenches
82
and second trenches
86
. However, since the film for polishing
88
, in forming, grows not only on the top surfaces of the dummy patterns
83
but also on the sidewalls inside of first trenches
82
, respective depositions for the film to lie on the dummy patterns
83
spread out horizontally to cover wider areas than underlying top surface areas of the dummy patterns. Therefore, even if the occupation density of the dummy patterns
83
has a prescribed value, a ratio (referred to as an occupation density of the film for polishing hereinafter) at which a total top surface area for raised sections of the film for polishing occupies the adjacent region
80
becomes different from the occupation density of the dummy patterns
83
.
As a result, when the C
Katsuki Nobuyuki
Ota Noriyuki
Katten Muchin Zavis & Rosenman
NEC Electronics Corporation
Picardat Kevin M.
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