Semiconductor device manufacturing: process – Forming bipolar transistor by formation or alteration of... – Using epitaxial lateral overgrowth
Reexamination Certificate
1999-06-16
2001-07-10
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Forming bipolar transistor by formation or alteration of...
Using epitaxial lateral overgrowth
C438S348000, C438S360000
Reexamination Certificate
active
06258686
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of semiconductor devices and to a semiconductor device. In concrete, the present invention relates to a manufacturing method of bipolar transistor semiconductor devices that is formed on a semiconductor substrate on which an isolation structure is formed with insulating layer, and to a bipolar transistor semiconductor device.
2. Description of the Related Art
FIG. 2A
,
FIG. 2B
,
FIG. 2C
,
FIG. 2D
,
FIG. 2E
,
FIG. 2F
,
FIG. 2G
, and
FIG. 2H
are diagrams showing one example of a manufacturing method of a existing bipolar transistor. The existing bipolar transistor B can be manufactured as shown in
FIG. 2A
with a semiconductor substrate
51
in which an isolation structure is formed by a first insulating layer
53
consisting of silicon oxide.
That is, all over a surface of the semiconductor substrate
51
, for instance, a substrate of a single crystal of p-type silicon, an impurity such as Sb or the like is implanted to form a collector electrode layer
52
. Above a surface of a central area thereof, an active area
54
of which upper surface is exposed is disposed and this active area is doped by an impurity of low concentration to form a collector layer. The surroundings of the collector layer is insulated and isolated from the surrounding elements or the like, for instance surrounding active areas, by a first insulating layer
53
that is formed by the use of, for instance, LOCOS method or the like.
Upon manufacturing a bipolar transistor B, first, a silicon layer
55
is formed all over the surface of the semiconductor substrate
51
by non-selective epitaxial growth method. Thereby, as shown in
FIG. 2B
, on the first insulating layer
53
a first poly-silicon layer
57
is formed to be a part of a base electrode. Simultaneously therewith, on an upper surface of the active area
54
a first epitaxial layer
56
is formed to be a base layer.
Further, all over the surface of the semiconductor substrate
51
a silicon oxide layer is formed to be an insulating layer. As shown in
FIG. 2C
, this insulating layer is patterned to form a second insulating layer
58
to be a buffer layer over from an upper surface of the first epitaxial layer
56
to an upper surface of the first poly-silicon layer
57
.
Next, as shown in
FIG. 2D
, all over the surface of the semiconductor substrate
51
, a second poly-silicon layer
59
that contains an impurity such as B or the like in high concentration is formed to be a base electrode. Further, on the second poly-silicon layer
59
a third insulating layer
60
consisting of silicon oxide and a fourth insulating layer
61
consisting of silicon nitride are stacked to be an interlayer film.
Thereafter, as shown in
FIG. 2E
, an opening for pulling out an emitter layer
66
is opened, while positioning it at an approximate center of the second insulating layer
58
, in the second poly-silicon layer
59
and the third and fourth insulating layers
60
and
61
by the use of anisotropic etching method. At this time, the opening
62
is opened to stop on the second insulating layer
58
.
Thereafter, as shown in
FIG. 2F
, on an inner surface of the opening
62
a fifth insulating layer
63
is formed with silicon nitride. Then, another opening
64
is opened in the second insulating layer
58
by the use of anisotropic etching method to expose a first epitaxial layer
56
.
Then, as shown in
FIG. 2G
, a third poly-silicon layer
65
that becomes an emitter electrode layer and contains an impurity such as Sb or the like in high concentration is formed inside the openings
62
and
64
so that a part thereof is positioned on an upper surface of the fourth insulating layer
61
. Thereafter, thermal treatment is applied to form an emitter layer
66
inside the first epitaxial layer
56
.
Finally, after a sixth insulating layer
67
consisting of silicon oxide is patterned all over the surface of the semiconductor substrate
51
, a wiring
68
for pulling out an emitter electrode (the third poly-silicon layer
65
) is formed. Thereby, a bipolar transistor B such as shown in
FIG. 2H
can be manufactured.
However, in a bipolar transistor B manufactured as described above, a base electrode layer is constituted of a first poly-silicon layer
57
that contains impurity of low concentration and a second poly-silicon layer
59
that contains impurity of high concentration. A base layer (the first epitaxial layer
56
) has a structure to pull out through connection with the first poly-silicon layer
57
formed in the surroundings thereof.
The first poly-silicon layer
57
is, being formed on the first insulating film
53
by the use of non-selective epitaxial growth method, a polycrystalline layer. Moreover, since impurity concentration thereof can not be made high, a base resistance becomes substantially high. As a result of this, the transistor is retarded in operation of high speed and power consumption thereof increases.
Further, when an opening
62
is formed to pull out an emitter layer
66
, if there occurs a discrepancy in alignment of a mask during photolithography, the opening
62
is formed at a position deviated from the center of the area of the second insulating layer
58
. As a result of this, there is a concern that an emitter layer
66
that is formed later is liable to approach or connect electrically to the first poly-silicon layer
57
that is a base electrode layer. Accordingly, there is a problem that an withstand voltage deteriorates and leakage occurs between base-emitter.
In particular, since the opening
62
is preferable to be formed at an approximately identical area with an active area
54
and a base layer is formed only on an upper surface of the active area
54
, a precise alignment of a mask is required. In addition, when a semiconductor device is made small, the active area is required to be small, and this is an increasingly important problem.
Further,
FIG. 3A
,
FIG. 3B
,
FIG. 3C
,
FIG. 3D
,
FIG. 3E
,
FIG. 3F
, and
FIG. 3G
are diagrams showing another existing manufacturing method of a bipolar transistor.
A base electrode layer of a bipolar transistor C manufactured according to the manufacturing method is, as shown in
FIG. 3G
, constituted so that it is pulled out from an upper surface of the base layer. The bipolar transistor C can be, as shown in
FIG. 3A
as identical as the aforementioned bipolar transistor B, manufactured with a semiconductor substrate
71
on which an isolation structure is formed with a first insulating layer
73
consisting of silicon oxide.
First, as shown in
FIG. 3B
, all over the semiconductor substrate
71
a second insulating layer
75
is formed to form a buffer layer. Then, on an upper surface of the second insulating layer
75
a first poly-silicon layer
76
that is a base electrode layer containing impurity in high concentration, a third insulating layer
77
that consists of silicon oxide and is an interlayer film, and a fourth insulating layer
78
consisting of silicon nitride are stacked.
Thereafter, as shown in
FIG. 3C
, an opening
79
for pulling out an emitter layer
83
is opened, while positioning on an approximate center of the active area
74
, in the first poly-silicon layer
76
, a third insulating layer
77
, and a fourth insulating layer
78
by the use of anisotropic etching method. At this time, the opening
79
is stopped on the second insulating layer
75
.
Then, as shown in
FIG. 3D
, on an inner surface of the opening
79
a fifth insulating layer
80
consisting of silicon nitride is formed. Thereafter, the second insulating layer
75
is etched to form a cavity
81
inside the second insulating layer
75
and expose the active area
74
.
Thereafter, as shown in
FIG. 3E
, inside the cavity
81
an epitaxial growth layer
82
is formed by the use of epitaxial growth method to form a base layer.
Then, as shown in
FIG. 3F
, a second poly-silicon layer
84
containing impurity such as Sb or the like in high concentration is formed inside the
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
Lattin Christopher
Niebling John F.
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