Manufacturing method of semiconductor device

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S749000

Reexamination Certificate

active

07119022

ABSTRACT:
In the manufacturing method of a GOLD structured TFT having a gate electrode of double-layered structure, in which, compared to a second layer gate electrode, the first layer gate electrode is thinner in film thickness and longer in dimension of the channel direction, by controlling the density of the photo-absorbent contained in a positive type resist such as diazonaphthoquinone (DNQ)-novolac resin series, the taper angle of the side wall is controlled to a desired angle range so that the angle thereof becomes smaller. Owing to this, it is possible to control the retreat amount of the resist when carrying out dry etching and the dimension of Lovarea to a desired dimensional range so that the dimension thereof becomes larger.

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Hatano, M. et al, “A Novel Self-Aligned Gate-Overlapped LDD Poly-Si TFT with High Reliability and Performance,” International Electron Devices Meeting, Washington DC, Dec. 7-10, 1997,IDEM Technical Digest, 97pp. 523-526, (1997).

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