Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2006-09-19
2006-09-19
Lindsay, Jr., Walter L. (Department: 2812)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S737000, C438S687000
Reexamination Certificate
active
07109127
ABSTRACT:
The present invention provides a method for preventing the defect the in shape of via holes cased when an alumina mask is used for the dry etching of an interlayer insulator composed of an SiOC film in the dual damascene process in which via holes are formed prior to forming wiring trenches. That is, after forming an alumina mask on an interlayer insulator composed of a low-k SiOC film via a cap insulator, the cap insulator and the interlayer insulator are dry-etched with using a photoresist film as a mask to form via holes. Next, after removing the photoresist film, the inside of the via holes are cleaned by using dilute hydrofluoric acid solution to remove alumina residue. Thereafter, the cap insulator and the interlayer insulator are dry-etched with using the alumina mask as a mask to form wiring trenches.
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Korean Official Action, dated Feb. 2, 2006, for No. 10-2004-0089195.
Aoki Hideo
Hotta Shoji
Noguchi Junji
Oshima Takayuki
Antonelli, Terry Stout and Kraus, LLP.
Lindsay Jr. Walter L.
Renesas Technology Corp.
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