Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching
Reexamination Certificate
2002-07-30
2004-06-08
Dang, Phuc T. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Vapor phase etching
C438S749000
Reexamination Certificate
active
06746965
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a semiconductor device having a circuit composed of a thin film transistor (hereafter, referred to as TFT), and in particular to a manufacturing method of a semiconductor device having a gate electrode wiring of a forwardly tapered shape which is obtained by photolithography processing and dry etching processing.
2. Related Art
Recently, electrooptical devices such as active matrix type liquid crystal display device, which performs active matrix display using a TFT, have been drawing public attention. The electrooptical device, which performs active matrix display, is provided with a TFT switch to each electrooptical device and state of crystal orientation of TN (abbreviation of Twisted-Nematic) mode can be utilized. Compared to a passive matrix display, since the active matrix display has advantages in the points of response speed, angle of visibility and contrast, it has become a major trend in the current notebook-sized personal computers, liquid crystal TVs and the like.
Generally, in the TFT, amorphous silicon or polycrystalline silicon is used as the channel layer thereof. Particularly, the polycrystalline silicon TFT, which is manufactured by means of low-temperature processing (generally, lower than 600° C.), is in a trend of being reduced in price and being enlarged in size. Electron or positive hole of the polycrystalline silicon TFT has large electric field mobility. Accordingly, when the TFT is used in a liquid crystal display device, since it is possible to integrate not only the transistor for pixel but also the driver, which is a peripheral circuit thereof, each maker of liquid crystal display device has promoted its development. However, when the polycrystalline silicon TFT is driven for a long period of time, sometimes such problems concerning reliability that decrease of mobility or ON-current (current which flows when the TFT is ON), increase of OFF-current (current which flows when the TFT is OFF) or the like are found. These phenomena are called as hot carrier effect, and it is known that these phenomena are caused by hot carrier that is generated due to high electric field in the area adjacent to the drain.
On the other hand, in MOS transistor of 1.5 &mgr;m in design rule, as a technique for buffering the OFF-current and the high electric field adjacent to the drain, an LDD (abbreviation of Lightly-Doped-Drain) structure is adopted. The LDD structure of NMOS transistor is formed by providing an n-type low-density impurity area (n−area) to the edge area of the drain using the side wall of the gate to provide a taper to the density of the impurity of the drain junction, and thereby, the concentration of electric field in the area adjacent to the drain is buffered. However, compared to the single drain structure, in the LDD structure, although the drain withstand voltage is considerably increased, since the resistance of the n−area is large, such disadvantage that drain current is decreased remains. Further, high electric field area exists under the side wall, the collision electrolytic dissociation reaches the maximum there, and hot electron is injected into the side wall. As a result, such problems of deterioration mode peculiar to the LDD that the n−area is depleted, and further, resistance is increased have emerged. Since the above-described problems have emerged accompanying the reduction of channel length, in the NMOS-transistor of 0.5 &mgr;m or less, GOLD (abbreviation of Gate-Overlapped-LDD) structure, in which the n−area is formed being overlapped with the edge area of the gate electrode, has been developed as a structure for solving the problem, and is now promoted to put into the actual mass production.
Under such circumstances as described above, in the n-channel polycrystalline silicon TFT also, in order to buffer the high electric field in the area adjacent to the drain, it is considered to apply the GOLD structured TFT. For example, an example of the application of the GOLD structured TFT is disclosed in IEDM97 TECHNICAL DIGEST; P523-526, 1997; Mutuko Hatano, Hajime Akimoto and Takesi Sakai. In the above-described GOLD structured TFT, the side wall for LDD of the polycrystalline gate is formed with polycrystalline silicon, and in the active layer comprised of poly-crystalline silicon layer immediately under the side wall for LDD, a low-density impurity area(n−area), which functions as the electric field buffer area, is formed. Further, at the outside area of the low-density impurity area (n−area), a high-density impurity area (n+area), which functions as the source area and drain area, is formed. As described above, in the GOLD structured TFT, it is characterized by that the low-density impurity area (n−area) is formed being overlapped with the edge area of the gate electrode.
In the manufacturing method of a GOLD structured TFT, as for the method of forming the high-density impurity area (n+area) and the low-density impurity area (n−area), a method in which the impurity areas are formed with resist mask only; and another method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching are known. In the former method in which the impurity areas are formed using the resist mask only, since the photolithography process for forming the resist mask is required to carry out twice, the increase in photolithography processes is a large disadvantage. On the other hand, in the latter method in which, using the gate electrode as the mask, the impurity areas are formed in a manner of self-matching, such an advantage that the photolithography process is prevented from increasing is provided, and that is advantageous for mass production processing.
As described above, in the polycrystalline silicon TFT, the GOLD structured TFT is taken into consideration. And as for the processing of the gate electrode of the GOLD structured TFT, the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, which is generally used in semiconductor processing, and the etching process by means of dry etching are taken into consideration.
In the photolithography process using a positive type resist of diazonaphthoquinone (DNQ)-novolac resin series, as the preventive measures against halation phenomenon, conventionally, a method in which a photo-absorbent composed of dye is added to the resist material is known. The halation phenomenon is a phenomenon, in which the resist in unexposed area is locally exposed undesirably by the reflected light from the tapered shoulder portion of the high reflective base substrate resulting in a local thinness of the resist pattern. When adding the photo-absorbent to the resist material to prevent the halation phenomenon, if the added amount of the photo-absorbent is too small, the preventive effect against the halation phenomenon cannot be obtained satisfactorily. On the other hand, if the added amount of the photo-absorbent is too large, although the preventive effect against the halation phenomenon can be obtained satisfactorily, the absorbance of the resist material becomes too large resulting in such disadvantage that the taper angle of the side wall of the resist pattern decreases. Accordingly, when the photo-absorbent is added to the resist material as the preventive measures against the halation phenomenon, it is necessary to control the density of the photo-absorbent to an adequate level.
Referring to
FIG. 5-F
and
FIG. 6-F
showing an example of a GOLD structured TFT respectively, the GOLD structured TFT is constituted of a gate electrode which is comprised of a first layer gate electrode and a second layer gate electrode on the above-described first layer gate electrode. Compared to the second layer gate electrode, the first layer gate electrode is characterized in that it is formed thinner in film thickness and longer in dimension of the channel direction. The GOLD st
Suzawa Hideomi
Uehara Ichiro
Cook Alex McFarron Manzo Cummings & Mehler, Ltd.
Dang Phuc T.
Semiconductor Energy Laboratory Co,. Ltd.
LandOfFree
Manufacturing method of semiconductor device does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method of semiconductor device, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method of semiconductor device will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3363980