Manufacturing method of semiconductor device

Semiconductor device manufacturing: process – Chemical etching – Vapor phase etching

Reexamination Certificate

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C438S637000, C438S669000, C438S695000, C438S706000, C438S733000, C257S774000, C257SE21218, C257SE21221, C257SE21222

Reexamination Certificate

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07981804

ABSTRACT:
A method of forming a metal interconnection that has a favorable cross-sectional shape is provided without the fear of side etching, even in a sparse arrangement of metal interconnections. The method, the following structure is employed. A region for placing a dummy metal interconnection is provided close to a region in which a metal interconnection is formed. A trench is formed in the dummy metal interconnection region and a resist pattern for the metal interconnection is then formed, giving the resist above the trench a large surface area per unit area. The metal interconnection is subsequently formed by dry etching in which an organic component from the resist above the trench forms a solid sidewall protection film, permitting anisotropic etching. The metal interconnection can thus have a favorable cross-sectional shape.

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patent: 2007/0132105 (2007-06-01), Akram et al.
patent: 2007/0187362 (2007-08-01), Nakagawa et al.
patent: 2009/0085120 (2009-04-01), Lu et al.
patent: 63-250823 (1988-10-01), None
patent: 63250823 (1988-10-01), None
patent: 7-45590 (1995-02-01), None

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