Manufacturing method of semiconductor device

Semiconductor device manufacturing: process – Packaging or treatment of packaged semiconductor – Insulative housing or support

Reexamination Certificate

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C438S107000, C438S123000, C438S124000, C438S508000

Reexamination Certificate

active

08048722

ABSTRACT:
Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device. Package substrate3by which ring shape common wiring3pfor electric supply was formed in the inner area of bonding lead3jin device region3vof main surface3ais used. Since a plurality of first plating lines3rand fourth plating lines3ufor electric supply connected to common wiring3pcan be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface3aof package substrate3, and the back surface. Even if the land part of plural lines is formed covering the perimeter of the back surface, electrolysis plating can be performed to the all land parts. As a result, electrolysis plating can be performed to a wiring, aiming at the increasing of pin count of a semiconductor device.

REFERENCES:
patent: 7408252 (2008-08-01), Shimanuki
patent: 7531441 (2009-05-01), Kado et al.
patent: 2004/0026767 (2004-02-01), Sato et al.
patent: 2006/0017151 (2006-01-01), Yoon et al.
patent: 2002-050715 (2002-02-01), None
patent: 2005-079129 (2005-03-01), None

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