Manufacturing method of semiconductor device

Details Manufacturing method of semiconductor device Manufacturing method of semiconductor device

2007-06-07

2010-02-09

Le, Dung A. (Department: 2818)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Making plural separate devices

C438S111000, C438S613000, C438S617000

Reexamination Certificate

active

07659146

ABSTRACT:
Performing electrolysis plating to a wiring is made possible, aiming at the increasing of pin count of a semiconductor device.Package substrate3by which ring shape common wiring3p for electric supply was formed in the inner area of bonding lead3j in device region3v of main surface3a is used. Since a plurality of first plating lines3r and fourth plating lines3u for electric supply connected to common wiring3p can be arranged by this, the feeder for electrolysis plating can be arranged to all the land parts on the back. Hereby, it becomes possible to perform electrolysis plating to the wiring of main surface3a of package substrate3, and the back surface. Even if the land part of plural lines is formed covering the perimeter of the back surface, electrolysis plating can be performed to the all land parts. As a result, electrolysis plating can be performed to a wiring, aiming at the increasing of pin count of a semiconductor device.

REFERENCES:
patent: 7408252 (2008-08-01), Shimanuki
patent: 2004/0026767 (2004-02-01), Sato et al.
patent: 2002-050715 (2002-02-01), None
patent: 2005-079129 (2005-03-01), None

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