Manufacturing method of self-aligned GaAs FET using refractory g

Details Manufacturing method of self-aligned GaAs FET using refractory g Manufacturing method of self-aligned GaAs FET using refractory g

1991-12-26

1993-07-06

Quach, T. N.

Fishing, trapping, and vermin destroying

437177, 437178, 437192, 437912, H01L 21338

Patent

active

052253600

ABSTRACT:
There is disclosed a manufacturing method of self-aligned GaAs FET using refractory gate with dual structure, the manufacturing method of the invention comprising the steps of: forming first photoresist pattern on a GaAs substrate to define an active region and ion-implanting n type impurity in the active region of the GaAs substrate; sequentially depositing a nitrogen-containing silicon layer and a metal layer on the substrate after removal of the first photoresist pattern; forming second photoresist pattern on the metal layer to define a gate; removing the silicon and metal layers using the second photoresist pattern as a gate mask to form the gate with dual structure of the silicon and metal layers; forming third photoresist pattern on the substrate to define source/drain regions after removal of the second photoresist pattern, and ion-implanting high-density impurity in the source/drain regions using the third photoresist pattern and the gate as a source/drain mask; annealing the substrate to make the silicon layer as upper side of the gate into metal-silicon-nitride material, and to make bottom portion of the metal layer as lower side of the gate into metal-silicon-nitride material; and forming ohmic contacts on the source/drain regions, respectively. A GaAs FET according to the invention is provided with a gate having low-resistance and improved schottky characteristics.

REFERENCES:
patent: 4804635 (1989-02-01), Young
patent: 4965218 (1990-10-01), Geissberger et al.
Ghandhi, S. K., VLSI Fabrication Principles, 1983, John Wiley & Sons, pp. 435-439.

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