Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Including dielectric isolation means
Reexamination Certificate
2002-02-27
2003-03-11
Lee, Eddie (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Including dielectric isolation means
C257S349000, C257S353000, C257S354000, C257S501000, C257S506000, C257S510000
Reexamination Certificate
active
06531754
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-401999, filed Dec. 28, 2001, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a manufacturing method of a partial SOI wafer, a semiconductor device using the partial SOI wafer and a manufacturing method thereof and more particularly to a manufacturing method of a partial SOI wafer having a non-SOI region formed therein by removing a BOX (Buried OXide) layer and silicon layer on a partial region of an SOI (Silicon On Insulator) substrate, a semiconductor device having elements formed in an SOI region and non-SOI region of the partial SOI wafer and a manufacturing method thereof.
2. Description of the Related Art
A DRAM including memory cells each having one MOSFET and one capacitor is suitable high density integration and is used in various applications as an inexpensive large-capacity memory. Particularly, in recent years, it is strongly required to develop a system LSI which is configured by integrating the DRAM and a logic circuit on a single semiconductor chip to enhance the system performance.
On the other hand, in order to enhance the performance of the logic circuit configured by mainly using MOSFETs, much attention is given to a structure in which MOSFETs are formed not in a silicon substrate, which is widely used in the prior art, but in a thin-film SOI substrate, and products are already available for some applications as high-performance logic devices.
Particularly, demand for a system LSI having the high-performance logic circuit and DRAM mounted thereon is strong and it is desired to develop the technique for forming the DRAM together with the logic circuit whose performance is enhanced by use of the SOI structure. In this trend, it is strongly required to develop a system LSI having a DRAM mounted on a high-performance logic chip configured by use of the SOI structure.
In order to meet the above requirement, it is considered that the above elements are selectively formed on an SOI wafer having an SOI region and a non-SOI region (a region formed by partially removing a BOX layer of the SOI substrate).
However, although a MOSFET formed on the SOI substrate has a bright future as a high-performance logic device, it is known that a parasitic MOSFET or parasitic bipolar transistor is operated depending on the source-drain voltage condition due to a so-called substrate-floating effect when gate voltage which turns OFF the MOSFET is applied and a leak current flows in the source-drain path. The above characteristic causes a problem of, for example, deterioration of retention for applications in which the specification for the leak current is strict, as in a memory cell transistor of a DRAM, for example, and is not preferable. Further, in the sense amplifier circuit of a DRAM, since the threshold voltages of the paired transistors are shifted due to the substrate-floating effect, the sense margin is lowered. Due to the above problems, it is difficult to form a DRAM with the same MOSFET structure as the high-performance logic circuit on the SOI substrate.
In order to completely cancel the substrate-floating effect, it is necessary to form a contact region and a lead-out region from the body section of each MOSFET and control the body potential. However, in order to meet the above requirement, the cell area and the area of the sense amplifier section are made extremely large, thereby losing the high integration density which is the best feature of a DRAM.
In order to solve the above problem, various methods for using a substrate (which is hereinafter referred to as a partial non-SOI wafer) obtained by forming a non-SOI region in an SOI substrate, forming a high-performance logic circuit on the SOI region and forming a circuit which is affected by the substrate-floating effect on the non-SOI region are proposed. The isolation technique by use of an STI (Shallow Trench Isolation) region for isolation between the SOI region and the non-SOI region of the partial SOI wafer is proposed with much attention paid to the depth of the BOX layer and the depth of the STI region (for example, Jpn. Pat. Appln. KOKAI Publication No. 08-17694), but a connection structure between the BOX layer and the STI region is not described.
The volume of an oxide existing on a chip formed by use of a silicon balk wafer is much smaller than the volume of silicon, since the oxide contains only a buried oxide in the STI region except the gate oxide film. On the other hand, the volume of oxide in the partial SOI wafer becomes equal to the volume thereof in the “BOX layer+STI region” and is much larger than the volume of the oxide in the bulk wafer. Therefore, the stress applied to the silicon layer becomes larger accordingly and crystal defects tend to occur in the non-SOI region. Further, since the STI region lies in the end portion of the oxide with the large volume, particularly, in a case where the BOX layer and STI region are continuously formed, crystal defects tend to occur in the non-SOI region and it is difficult to obtain a high-quality partial SOI wafer unless much attention is paid to the shape thereof.
As described above, with the conventional partial SOI wafer manufacturing method, crystal defects tend to occur in the non-SOI region and the quality thereof is lowered by concentration of the stress due to a difference in the volume of the oxide between the SOI region and the non-SOI region.
Further, in the conventional semiconductor device using the partial SOI wafer and the manufacturing method thereof, the integration density is lowered if an attempt is made to attain high speed operation and high performance.
BRIEF SUMMARY OF THE INVENTION
According to an aspect of the present invention, there is provided a semiconductor device comprising a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an insulating layer for isolation buried in the trench, wherein an angle made by the bottom surface of the insulating layer for isolation and the side surface of the second semiconductor region is an obtuse angle.
According to another aspect of the present invention, there is provided a semiconductor device comprising a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an insulating layer for isolation buried in the trench, wherein a portion near a contact portion of the bottom surface of the insulating layer for isolation with the second semiconductor region has a curved surface.
According to another aspect of the present invention, there is provided a partial SOI wafer manufacturing method comprising selectively removing part of a buried oxide layer and a first silicon layer on an SOI substrate having the first silicon layer formed on a semiconductor substrate with the buried oxide layer disposed therebetween, forming a protection film to cover a remaining portion of the first silicon layer, forming a second silicon layer by use of an epitaxial growth method on that part of the semiconductor substrate from which the first silicon layer and buried oxide layer are removed, forming a trench to reach at least the buried oxide layer in a boundary portion between the first and second silicon layers by anisotropic etching, and burying an isolation insulating material into the trench, wherein an angle made by the bottom surface of the trench with the side surface of the second silicon layer is an obtuse angle or a portion near a contact portion of the bottom
Fujii Osamu
Mizushima Ichiro
Nagano Hajime
Sato Tsutomu
Yamada Takashi
Fenty Jesse A.
Kabushiki Kaisha Toshiba
Lee Eddie
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