Fishing – trapping – and vermin destroying
Patent
1993-10-27
1995-04-25
Chaudhuri, Olik
Fishing, trapping, and vermin destroying
437 44, 437 57, 437247, 257338, 257351, H01L 21265
Patent
active
054098475
ABSTRACT:
Gate electrodes of an N-channel transistor and a P-channel transistor are formed on a semiconductor substrate with a gate insulator therebetween. After conducting a first thermal treatment to the gate electrodes, N-type heavily doped diffusion layers to be a source or a drain of the N-channel transistor are formed using the gate electrode of the N-channel transistor as a mask. After conducting a second thermal treatment to the N-type heavily doped diffusion layers at a lower temperature than that of the first thermal treatment, P-type heavily doped diffusion layers to be a source or a drain of the P-channel transistor are formed using the gate electrode of the P-channel transistor as a mask. Then, a third thermal treatment is conducted to the P-type heavily doped diffusion layers at a lower temperature than that of the second thermal treatment.
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Hori Atsushi
Kato Yoshiaki
Masuda Hiroshi
Matsuo Ichiro
Nakabayashi Takashi
Chaudhuri Olik
Matsushita Electric - Industrial Co., Ltd.
Pham Long
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