Manufacturing method of active matrix substrate

Details Manufacturing method of active matrix substrate Manufacturing method of active matrix substrate

2001-07-11

2004-05-25

Norton, Nadine G. (Department: 1765)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S707000, C438S708000, C438S717000, C438S725000, C257S057000, C257S079000

Reexamination Certificate

active

06740596

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method of a liquid crystal display panel which uses thin film transistors (TFTs), and in particular, to a manufacturing method of an active matrix substrate.
2. Description of the Prior Art
In an active matrix substrate which uses TFTs used for a liquid crystal display panel etc., and in particular, inverted stagger type TFTs as active elements, pairs of the above-described TFT and a corresponding liquid crystal to each TFT are arrayed in a matrix as pixels all over the substrate except a peripheral area of a glass substrate. Gate terminals each connecting with a drive IC, and data terminals (drain terminals) are provided on the peripheral area of the glass substrate. Furthermore, protection transistors against static electricity are connected to these terminal portion so as to perform the protection against overcurrent or overvoltage from the outside of the active matrix substrate as a measure against ESD (Blectro-Static-Discharge).
Hereinafter, the prior art will be described with reference to
FIG. 2
that is a circuit diagram of an active matrix substrate. As shown in
FIG. 2
, plenty of gate terminals G and drain terminals D are formed in the periphery of the active matrix substrate. Gate wirings
401
including gate bus wirings and drain wirings
402
including data wirings and drain bus wirings are arrayed in a matrix toward the internal area of the active matrix substrate from the gate terminals G and drain terminals D respectively. ESD protection circuits
403
and
503
are formed adjacent to each gate terminal G and each drain terminal D.
Each of the ESD protection circuits
403
consists of two thin film transistors. In one TFT a gate electrode and a drain electrode are connected to a gate wiring
401
. The source electrode is connected to a common wiring of a common terminal COM. The common wiring is simultaneously formed in the same layer as that of the drain wirings
402
. On the other hand, the gate electrode and source electrode of another TFT are connected to the common wiring while its drain electrode is connected to the gate wiring
401
.
Similarly, in one TFT constituting the ESD protection circuit
503
, the gate electrode and drain electrode are connected to the drain wiring
402
. The source electrode thereof is connected to a wiring of a dummy terminal. This wiring is simultaneously formed in the same layer as that of the gate wirings
401
. The gate electrode and source electrode of another TFT constituting the ESD protection circuit
503
are connected to a wiring of the dummy terminal. The drain electrode thereof is connected to the drain wiring
402
. The gate wiring
401
of the gate terminal G is connected to the gate electrode of a switching transistor
404
constituting a pixel. The drain wiring
402
of the drain terminal D is connected to the drain electrode of the switching transistor
404
. In addition, the source electrode of this switching transistor
404
is connected to a transparent pixel electrode of a liquid crystal shown in FIG.
2
. In this case, a vertical electric field is applied to the liquid crystal, and hence, the liquid crystal is called a TN (Twist Nematic) liquid crystal.
In an ESD protection circuit formed in a peripheral area of an active matrix substrate as described above, a TFT constituting the ESD protection circuit must have electric connection between two different conductive layers, one of which comprises a gate electrode, a gate bus wiring and a wiring of a dummy terminal, and the other of which comprises a drain electrode, a drain bus wiring and a wiring of a common terminal COM.
Next, a manufacturing method of an active matrix substrate having the electric connection will be described with reference to FIGS.
1
(
a
) to
1
(
e
).
FIGS.
1
(
a
) to
1
(
e
) are typical cross sectional views in the order of manufacturing process steps in the case where the connection of the gate electrode and drain electrode of a TFT is performed, the connection becoming indispensable as a measure against ESD.
As shown in FIG.
1
(
a
), the gate electrode
406
is formed on the glass substrate
405
, which is a transparent insulating substrate, by patterning a layer of metal such as chromium. Then, a gate insulation layer
407
, an amorphous silicon film
408
, and an n+amorphous silicon film
409
are deposited in order so that the gate electrode
406
may be covered by the gate insulation layer
407
.
As shown in FIG.
1
(
b
), a resist mask
410
is formed by photolithography technology, and the n+amorphous silicon film
409
and amorphous silicon film
408
are patterned by dry etching technology. Then, a semiconductor layer
411
, which is an amorphous silicon layer, and an n+amorphous silicon layer
412
are formed.
The resist mask
410
is removed and a conductive film consisting of chromium or the like is deposited on the entire surface by sputtering.
As shown in FIG.
1
(
c
), a resist mask
413
is formed and the metal conductive film is patterned into a predetermined shape by dry etching technology.
Thus, as shown in FIG.
1
(
c
), the source electrode
414
and drain electrode
415
are formed. Then, the resist mask
413
is removed, and the n+amorphous silicon layer
412
is patterned by utilizing the source electrode
414
and drain electrode
415
as etching masks. Thus, a source ohmic layer
416
and a drain ohmic layer
417
are formed on an end portion of the semiconductor layer
411
.
As shown in
FIG. 1
(
d
), a passivation film
418
is deposited on the entire surface and a resist mask
419
is formed thereon, and contact holes
420
and
421
are formed in the passivation film
418
on the gate electrode
406
and drain electrode
415
by using etching technology respectively.
The resist mask
419
is removed, and as shown in Fig.
1
(
e
), the gate electrode
406
and drain electrode
415
are electrically connected to each other by a transparent metal electrode
422
through the contact holes
420
and
421
. Thus, as shown in FIG.
1
(
e
), an inverted stagger type TFT with the gate electrode
406
and drain electrode
415
being electrically connected to each other is formed on the glass substrate
405
.
When an active matrix substrate having ESD protection circuits is produced by using a conventional electric connection method as described above, at least five photolithography process steps are needed. Concerning photolithography process steps used in the active matrix substrate having ESD protection circuits the technology four photolithography process steps is shown in Japanese Patent Laid-Open No. 63-015472 as an example. In this publication, a semiconductor layer and a source/drain electrode of an inverted stagger type TFT, and a transparent metal electrode connected to the source/drain electrode is formed under a passivation film by using only three photolithography steps. But a method of forming contact holes in the passivation film is not described.
Currently, it is indispensable that an active matrix substrate for an LCD has to have an ESD protection circuit as a measure against the ESD. For this purpose, it is necessary to electrically connect a gate electrode or a gate bus wiring with a drain electrode (or source electrode) or a drain bus wiring through a contact hole in the active matrix substrate with TFT.
However, as described above, when using the conventional technology, manufacture the active matrix substrate having an ESD protection circuit needs at least five photolithography process steps. Therefore, the manufacturing process of the active matrix substrate having an ESD protection circuit needs one more photolithography step than that of the active matrix substrate having no ESD protection circuit.
Such increase in photolithography process steps brings about the reduction of a manufacturing yield of LCDs inevitably, and reduces productivity thereof. Then, the manufacturing cost of LCDs increases and reliability thereof is also lowered.
SUMMARY OF TEE INVENTION
A

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