Electric lamp or space discharge component or device manufacturi – Process – With assembly or disassembly
Reexamination Certificate
2002-09-20
2004-05-11
Ramsey, Kenneth J. (Department: 2879)
Electric lamp or space discharge component or device manufacturi
Process
With assembly or disassembly
C445S049000, C445S050000, C445S051000, C430S311000, C430S314000
Reexamination Certificate
active
06733355
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a manufacturing method for a triode field emission display, and more particularly, to a manufacturing method for a triode field emission display, in which the field emission display provides a large screen size and has holes that are minutely and uniformly formed.
BACKGROUND OF THE INVENTION
In the first field emission displays (FEDs), conical metal microtips were formed on cathode electrodes, and gate electrodes were formed in peripheries of the metal microtips. With such a structure, electrons emitted from the metal microtips are accelerated toward a phosphor layer provided on anode electrodes to thereby realize images. However, a drawback of this configuration is that expensive semiconductor equipment is needed to form the metal microtips (i.e., an electron-emitting layer). This increases overall manufacturing costs and makes the production of display devices of a large screen size difficult.
To remedy this problem, there has been disclosed an FED with a surface electron source structure, in which the electron emitting layer is formed as a film. Such a surface-type electron emitting layer is realized using a conventional carbon-based material. In recent times, much attention has been given to a carbon nanotube structure. Carbon nanotubes have the advantages of a minute curvature radius at their tips of approximately 100. and are capable of realizing smooth electron emission at driving voltages of approximately 10.50V. Accordingly, carbon nanotubes enable operation at low voltages, and are an ideal electron emitting source for FEDs with large screen sizes.
FEDs that use carbon nanotubes as the electron emitting source generally employ a triode structure having gate electrodes. In such FEDs, an insulation layer and gate electrodes are provided on cathode electrodes, holes are formed to expose the cathode electrodes through the insulation layer and gate electrodes, then a carbon nanotube electron emitting layer is formed within the holes and on the cathode electrodes.
In the above processes, the insulation layer having the holes may be formed by a thin film process such as the PECVD (plasma enhanced chemical vapor deposition) process or by a thick film process using paste printing. However, problems result in either of the two types of processes that interfere with the manufacture of the triode FED.
In particular, when forming the insulation layer using the thin film process, although it is possible to obtain a film having superior insulating characteristics, it is difficult to realize a sufficient thickness for the film, that is, a thickness at least matching that of the electron emitting layer. Further, even if an adequate thickness for the insulation layer is realized using the thin film process, the time required for the process is long, it is necessary to control the stresses within the film, and a complicated etching process is required to make the thick film uniform when forming the holes.
In the case where the insulation layer is formed using the thick film printing process, although it is easy to realize a desired thickness, there are difficulties in making the holes uniform and adequately minute as a result of the inherent characteristics of the printing method. When forming the holes in the insulation layer using the printing process, it is possible to realize an insulation layer having holes using only the printing process, and also to form the holes by an etching process after the insulation layer is printed and sintered. However, in either of the two printing processes to form the holes in the insulting layer, again it is possible to realize a desired thickness for the insulating but difficult to form the holes to a minute size.
SUMMARY OF THE INVENTION
It is one object of the present invention to provide a manufacturing method for a triode FED that enables the formation of an insulation layer provided between cathode electrodes and gate electrodes to a desired thickness, as well as the formation of holes in the insulation layer that are both uniform and minute.
In one embodiment, the present invention provides a method for manufacturing a triode FED comprising forming cathode electrodes on a first substrate; depositing a photosensitive material on the first substrate covering the cathode electrodes; patterning the photosensitive material in a predetermined pattern to form guide supports for the formation of insulation layer holes at locations where an electron emitting layer will be formed on the cathode electrodes; forming a preliminary insulation layer on the first substrate covering the guide supports; removing the guide supports from the cathode electrodes to form holes at the locations of the guide supports, thereby realizing a completed insulation layer from the preliminary insulation layer; forming gate electrodes on the insulation layer, the gate electrodes having holes corresponding to the holes of the insulation layer; forming an electron emitting layer on the cathode electrodes; providing a second substrate with anode electrodes and a phosphor layer formed thereon, substantially in parallel to the first substrate, and connecting and sealing the first and second substrates to realize a sealed assembly; and exhausting air from within the sealed assembly.
According to a feature of an embodiment of the present invention, the photosensitive material is selected from the group consisting of a DFR (dry film resist) film, polyimide, an emulsion, and a photoresist.
According to another feature of an embodiment of the present invention, the preliminary insulation layer is formed by using a printing process to deposit and dry an insulation paste on the first substrate covering the guide supports.
According to yet another feature of an embodiment of the present invention, the guide supports for the formation of insulation layer holes are formed by forming holes in the photosensitive material in a predetermined pattern using a photolithography process, and performing a plating process within the holes to form a plating layer therein, then removing the photosensitive material from the first substrate to thereby realize metal supports by the plating layer.
According to still yet another feature of an embodiment of the present invention, the removal of the guide supports is realized by removing an upper portion of the preliminary insulation layer to expose an upper end of the guide supports, and removing the guide supports by using one of a chemical etching process and an electrolysis process.
According to still yet another feature of an embodiment of the present invention, the guide supports for the formation of insulation layer holes are formed by patterning the photosensitive material using a photolithography process to thereby realize photosensitive supports obtained by the photosensitive material at locations where an electron emitting layer will be formed.
According to still yet another feature of an embodiment of the present invention, the exposure performed by the photolithography process is effected from a side of the first substrate opposite that on which the cathode electrodes are formed.
According to still yet another feature of an embodiment of the present invention, the removal of the guide supports is realized by sintering the preliminary insulation layer and removing portions of the preliminary insulation layer corresponding to positions of the guide supports.
According to still yet another feature of an embodiment of the present invention, the sintering is performed by maintaining a temperature that exceeds a softening point of an insulation frit by 20-30, for 5-60 minutes.
According to still yet another feature of an embodiment of the present invention, the preliminary insulation layer is formed by a process selected from the group consisting of a printing process, a cataphoresis process, a doctor blade process, and a spray process.
REFERENCES:
patent: 5053673 (1991-10-01), Tomii et al.
patent: 5320570 (1994-06-01), Kane
patent: 5529524 (1996-06-01), Jones
patent: 5551903 (1996-09-01), Kumar
Hwang Seong-Yeon
Kim Jong-Min
Lee Sang-Jin
McGuireWoods LLP
Ramsey Kenneth J.
Samsung SDI & Co., Ltd.
Santiago Mariceli
LandOfFree
Manufacturing method for triode field emission display does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Manufacturing method for triode field emission display, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Manufacturing method for triode field emission display will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3200720