Manufacturing method for semiconductor memory device having stac

Details Manufacturing method for semiconductor memory device having stac Manufacturing method for semiconductor memory device having stac

1992-06-10

1993-11-02

Thomas, Tom

Fishing, trapping, and vermin destroying

437 47, 437 60, 437 69, 437919, H01L 2170

Patent

active

052583210

ABSTRACT:
A semiconductor memory device having memory cells formed adjacent to each other comprises a P type semiconductor substrate having adjacent two trenches, a P.sup.+ impurity region formed in the side portions and the bottom portions of the trenches, n type first polysilicon layers serving as common electrodes formed in the upper portion of the P.sup.+ impurity region through an insulating film, second polysilicon layers formed inside and in the upper portion of the trenches formed of the first polysilicon layers through an insulating film, and a third polysilicon layer formed on the second polysilicon layers, only the third polysilicon layer constituting a connecting electrode between the adjacent memory cells.

REFERENCES:
patent: 4577395 (1986-03-01), Shibata
patent: 4855952 (1989-08-01), Kiyosumi
patent: 4855953 (1989-08-01), Tsakamoto et al.
patent: 4921816 (1990-05-01), Imo
IEEE Transactions on Electron Devices: "A Corrugated Capacitor Cell (CCC)", By H. Sunami et al, vol. ED-31, No. 6 Jun. 1984, pp. 746-753.

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