Fishing – trapping – and vermin destroying
Patent
1995-09-08
1998-11-03
Niebling, John
Fishing, trapping, and vermin destroying
437 52, H01L 218247, H01L 21265
Patent
active
058307710
ABSTRACT:
The insulating ability of a semiconductor device of two-layer gate electrode structure, such as EPROM, is improved at the upper surface of the first gate electrode as well as at the upper and lower edge parts of the first gate electrode. A LOCOS film is formed on a semiconductor substrate, and a floating gate is formed by patterning. Next, the first oxide film is formed on the floating gate, and then the first oxide film is etched out. Subsequently, the second oxide film is formed on the floating gate, and a control gate is formed on the floating gate using the second oxide film as an inter-layer insulating film. As a result of these two oxidations of the first and second oxide films and the removal of the first oxide film, the asperity of the upper surface of the floating gate is removed, and the upper and lower edge parts thereof are shaped into a round form.
REFERENCES:
patent: 4412310 (1983-10-01), Korsh et al.
patent: 4519849 (1985-05-01), Korsih et al.
patent: 5571736 (1996-11-01), Paterson et al.
patent: 5576233 (1996-11-01), Hutter et al.
Wolf et al., "Silicon Processing for the VLSI Era Vol. 1: Process Technology", Lattice Press, pp. 532-534, 1986.
Fukatsu Shigemitsu
Kubokoya Ryouichi
Kuroyanagi Akira
Booth Richard A.
Niebling John
Nippondenso Co. Ltd.
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