Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Reexamination Certificate
2003-04-30
2004-12-21
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
C438S221000, C438S435000
Reexamination Certificate
active
06833311
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a manufacturing method for semiconductor integrated circuits. More particularly, the present invention relates to a manufacturing method for a shallow trench isolation region with high aspect ratio.
2. Description of the Related Arts
Recently, as the manufacturing techniques for semiconductor integrated circuits develop, the number of elements in a chip increases. The size of the element decreases as the degree of integration increases. The line width used in manufacturing lines has decreased from sub-micron to quarter-micron, or even smaller. However, regardless of the reduction in size of the element, adequate insulation or isolation must be formed among individual elements in the chip so that adequate element characteristics can be achieved. This technique is called device isolation technology. The main object is to form an isolation region, and reduce the size of the isolation as much as possible while assuring good isolation to have more chip space for more elements.
Among different element isolation techniques, LOCOS and shallow trench isolation region manufacturing methods are the most commonly used. In particular, as the latter has a small isolation region and can keep the substrate level after the process, it is the semiconductor manufacturing method receiving the most attention. The conventional manufacturing method for a shallow trench isolation region comprises forming a dielectric layer to fill a trench on a substrate by chemical vapor deposition (CVD), and etching back the dielectric layer on the substrate to remove the redundant dielectric layer. However, as the density of the semiconductor integrated circuits increases and the size of the elements decreases, the above mentioned deposition experiences problems in step coverage and cannot completely fill the trench. This influences the isolation effect among elements.
High density plasma chemical vapor deposition (HDPCVD) has extremely good gap-filling ability and is suitable for fine shallow trench isolation region manufacturing. However, the oxide layer deposited by HDPCVD has a distinctive topography which has to be leveled by chemical mechanical polishing (CMP).
At present, the manufacturing method for a shallow trench isolation region usually utilizes HDPCVD for better step coverage in the trench. To further illustrate the process, the manufacturing method is shown in cross section in
FIGS. 1A
to
1
B.
As shown in
FIG. 1A
, a shield layer is formed on a substrate
10
. For example, a pad oxide layer
11
with a thickness of 50 Å to 200 Å is formed on a silicon substrate
10
by chemical vapor deposition (CVD) or thermal oxidation, and a silicon nitride layer
12
with a thickness of 1,200 Å to 1,700 Å is deposited on the pad oxide layer
11
by CVD. The pad oxide layer
11
and the silicon nitride layer
12
both form the shield layer. Next, a photoresist layer is coated on the silicon nitride layer
12
and patterned using photolithography to expose the portion where the element isolation region is to be formed. The silicon nitride layer
12
and the pad oxide layer
11
are etched sequentially using the photoresist layer as a mask. After the photoresist layer is removed with adequate liquid, the silicon nitride layer
12
and the pad oxide layer
11
are used as a mask to etch silicon substrate
10
, and a trench with a depth of 5000 Å to 6000 Å is formed for the isolation of elements.
Next, as shown in
FIG. 1B
thermal oxidation is performed to grow a thin oxide layer
14
with a thickness of 180Å~220 Å as a liner covering the bottom and sidewall of the trench. A thin silicon nitride layer
16
is then formed on the shield layer. After that, HDPCVD is performed, using, for example. O2 and SiH4 as reactants with Ar sputtering to deposit a silicon dioxide layer
18
as an insulation layer, and the trench Is filled as shown in FIG.
1
B. The silicon dioxide layer
18
has an undulate surface due to different densities of trench distribution and the characteristics of HDPCVD.
The manufacturing method for a high aspect ratio shallow trench isolation region presently has the drawback as shown in
FIGS. 1C and 1D
.
As shown in
FIG. 1C
, as the opening width of the trench narrows and/or the aspect ratio of the trench increases, for example the opening width may be less than 0.15 &mgr;m and/or the aspect ratio larger than 3, the silicon dioxide layer
18
deposited conventionally, using HDPCVD, may have voids
20
which result in poor insulation quality of the shallow trench isolation region.
In addition, as shown in
FIG. 1D
, debris
21
produced during Ar sputtering in HDPCVD may remain inside the trench, and this also results in void formation.
SUMMARY OF THE INVENTION
It is thus a primary object of the present invention to provide a manufacturing method for a shallow trench isolation region to improve the gap-filling ability of the insulation layer and isolation quality among elements.
In one aspect of the present invention, the manufacturing method for a shallow trench isolation region comprises providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by high density plasma chemical vapor deposition (HDPCVD), removing the majority of the first insulation layer outside the trench, and forming a second insulation layer on the first insulation layer by low pressure chemical vapor deposition (LPCVD) to fill the trench. With the manufacturing method for the present invention, a void-free shallow trench isolation region can be accomplished.
In another aspect of the present invention, the manufacturing method for a shallow trench isolation region comprises providing a substrate with a trench therein, forming a first insulation layer on the substrate and inside the trench by HDPCVD, removing the majority of the first insulation layer outside the trench, forming a second insulation layer on the first insulation layer and inside the trench by HDPCVD, removing the majority of the second insulation layer outside the trench, and forming a third insulation layer on the second insulation layer by LPCVD to fill the trench. With repeated steps of high density plasma chemical vapor deposition and etching, a trench with high aspect ratio, for example, with an aspect ratio larger than 3.5 or 4, or even 9 to 10, can be filled. After removing the insulation layer outside the trench, the trench is filled by LPCVD to prevent unwanted void formation in the shallow trench isolation region.
According to a preferred embodiment of the present invention, the first insulation layer is formed by HDPCVD using O
2
and SiH
4
as reactants with Ar sputtering. The insulation layer outside and on the sidewalls of the trench is spray-etched using a mix of HF and sulfuric acid as echant with a spray type oxide etchant for the subsequent LPCVD. The reactant for the final LPCVD is tetraethyloxysilane (TEOS).
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Ho Hsin-Jung
Ho Tzu En
Wu Chang Rong
Duong Khanh
Nanya Technology Corporation
Quintero Law Office
Zarabian Amir
LandOfFree
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