Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Patent
1993-09-17
1995-07-11
Jackson, Jerome
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
257773, 257618, 257510, 257296, H01L 2348, H01L 2944
Patent
active
054323819
ABSTRACT:
A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4") are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.
REFERENCES:
patent: 5043781 (1991-08-01), Nishiura et al.
patent: 5094900 (1992-03-01), Langley
IBM Technical Disclosure Bulletin, vol. 31, No. 2, Jul. 1988, "Process for Making Conductive Lines of Two Different Materials Within a Level of Wiring", (1988) pp. 34-35.
IEEE Journal of Solid-State Circuits, vol. SC-18, No. 3, Jun. 1983, "A 256 kbit ROM with Serial ROM Cell Structure", Roger Cuppens et al., pp. 340-344.
Symposion in VLSI Technology 1987, Japan, "A High Density 4Mbit dRAM Process Using a Fully Overlapping Bitline Contact (FoBIC) Trench Cell", by Kuesters et al, pp. 93-94.
Research Disclosure 32246, Anonomous, "Substrate Contact with Closed Bottom Trenches," Feb. 1991.
Guay John F.
Jackson Jerome
Siemens Aktiengesellschaft
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