Manufacturing method for a low voltage power MISFET utilizing on

Details Manufacturing method for a low voltage power MISFET utilizing on Manufacturing method for a low voltage power MISFET utilizing on

1992-11-13

1994-04-12

Chaudhuri, Olik

Fishing, trapping, and vermin destroying

437 41, 437203, 437228, 148DIG126, H01L 21265

Patent

active

053025377

ABSTRACT:
A manufacturing method for a low-voltage power MISFET which utilizes only three masks (photosteps). In the first step, a polysilicon layer (3) is structured and a cell field and edge zones are produced. An oxide layer (2) is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge (4) and the cells. A metal layer is then applied, this being interrupted between the cells and the edge (4) with the third photostep. Field plates and a channel stopper (9) are thus produced. As last step, a weakly conductive layer (20) is applied onto the entire surface.

REFERENCES:
patent: 4055884 (1977-11-01), Jambotkar
patent: 5087577 (1992-02-01), Strack
patent: 5179032 (1993-01-01), Quigg

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