Manufacture of semiconductor devices with Schottky barriers

Details Manufacture of semiconductor devices with Schottky barriers Manufacture of semiconductor devices with Schottky barriers

2002-07-19

2004-11-30

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Forming schottky junction

C438S573000, C438S576000, C438S578000, C257S471000, C257S473000

Reexamination Certificate

active

06825105

ABSTRACT:

This invention relates to methods of manufacturing semiconductor devices having a Schottky barrier between a Schottky electrode and a semiconductor body portion that is bounded laterally by a trenched insulated electrode. The invention also relates to such devices constructed in accordance with such manufacturing methods. The devices may be, for example trench-gate power MOSFETs (insulated-gate field-effect transistors), and/or, for example trenched Schottky rectifier diodes.
It is known from U.S. Pat. No. 4,521,795 (our ref: PHB32842) to integrate a Schottky barrier diode between the source and drain of a power MOSFET, i.e. in parallel with the p-n junction diode between the drain drift region and the channel-accommodating region of the MOSFET. The Schottky barrier is formed between part of the source electrode and a semiconductor body portion that forms part of the drain drift region. Such a parallel Schottky diode can serve to increase switching speed and reduce high dissipation, stored charge, and high switching losses that could otherwise result from conduction of the p-n junction diode when, for example, the MOSFET is switching inductive loads and/or serves as the control FET of a synchronous dc—dc converter. Thus, the Schottky diode has lower Vf than the p-n diode and should therefore take the current that would otherwise flow through the p-n diode. The whole contents of U.S. Pat. No. 4,521,795 are hereby incorporated herein as reference material.
U.S. Pat. No. 4,521,795 discloses embodiments in which the Schottky barrier terminates laterally in a guard ring formed by a part of the channel-accommodating region of the MOSFET. In addition to MOSFET embodiments of the planar DMOS type, U.S. Pat. No. 4,521,795 teaches the inclusion of such a Schottky barrier in a trench-gate MOSFET. In this latter case, the MOSFET trench-gate is an insulated electrode in a trench that laterally bounds a portion of the drift region that forms the Schottky barrier with the source electrode.
U.S. Pat. No. 4,646,115 (our ref: PHB33047) and U.S. Pat. No. 5,612,567 disclose discrete Schottky barrier rectifiers of advantageous construction. The Schottky barrier areas of these rectifiers are present between closely-spaced field relief means in the form of, inter alia, trenched insulated electrodes. The Schottky electrode forms the barrier areas with surface portions of a semiconductor drift region that are laterally bounded by the trenched electrodes. These trenched electrodes are electrically contacted by the Schottky electrode. The drift region may adjoin the trench over most of the depth of the trench and has a width and doping concentration sufficient for the drift region to be depleted in a blocking state of the Schottky-rectifier device. The whole contents of U.S. Pat. No. 4,646,115 and U.S. Pat. No. 5,612,567 are hereby incorporated herein as reference material.
Nowadays, in the manufacture of semiconductor devices, it is often desirable to use self-aligned techniques to fabricate the devices with compact geometries.
According to the present invention, there are provided methods of manufacturing such devices, wherein:
(a) a mask pattern is provided at a surface of a semiconductor body to mask an area where a Schottky barrier is to be formed,
(b) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window of the mask pattern, and a trenched insulated electrode is formed by etching a trench into the body at the narrow window and by providing insulating material and then electrode material in the trench,
(c) a guard region is provided by introducing dopant of the second conductivity type into the body via the wider window of the mask pattern, the mask pattern being sufficiently thick to mask the underlying body portion against the dopant introduction and sufficiently wide to prevent the dopant from extending laterally into the area where the Schottky barrier is to be formed, and
(d) at least the mask pattern is removed before depositing a Schottky electrode at least at the area where the Schottky barrier is to be formed.
Thus, the present invention uses these process steps (a), (b), (c) and (d) to self-align the guard region, the trenched insulated electrode and the Schottky barrier with respect to each other. By so using the wider and narrow windows as defined by the sidewall extensions, both a very narrow guard region and a very narrow insulated-electrode trench can be formed in a precise and self-aligned manner with respect to the Schottky barrier area. Furthermore, these process steps (a), (b), (c) and (d) may be used in various device contexts in a manner compatible with various device technologies to manufacture, for example, discrete Schottky rectifiers, discrete MOSFETs with integrated Schottkies, and integrated circuit devices.
One or more of the process steps (a), (b), (c) and (d) may also be used to provide other parts of the semiconductor device, so streamlining the manufacture. Thus, of particular benefit is the synergy possible between a method in accordance with the present invention and the advantageous method of manufacturing trench-gate MOSFETs disclosed in U.S. Pat. No. 6,087,224 (our reference PHB34245). In the method of U.S. Pat. No. 6,087,224:
(i) a narrow window is defined by providing sidewall extensions at the sidewalls of a wider window in a first mask at a surface of a semiconductor body,
(ii) a trench is etched at the narrow window into a body portion of the first conductivity type that provides a drain drift region of the device,
(iii) the trench-gate is provided as an insulated electrode in the trench, and
(iv) a source region of the first conductivity type is provided so as to be self-aligned with the trench-gate by means of the sidewall extensions.
The whole contents of U.S. Pat. No. 6,087,224 are hereby incorporated herein as reference material.
The sidewall extensions of step (i) may be formed in step (b). The guard region of the present invention may be formed simultaneously with at least a part of a channel-accommodating region of the U.S. Pat. No. 6,087,224 device, both regions being of the second conductivity type. A part of the source electrode (that contacts the source region) may comprise the Schottky electrode that contacts a surface-adjacent part of the drain drift region. The process steps (a), (b), (c) and (d) of the present invention may be combined into various forms of the U.S. Pat. No. 6,087,224 method. Thus, for example, the source region and/or channel-accommodating region (and hence the guard region) may be provided either before or after forming the trench-gate, either a deep or shallow highly-doped region may be provided (also in a self-aligned manner) in the channel-accommodating region (but masked from the Schottky barrier area), either a doped-semiconductor or a metal or silicide material may be used for the gate, and either a deposited or grown insulating overlayer may be provided (also in a self-aligned manner) over the trench-gate.
The MOSFET may be a cellular device that comprises at least one Schottky cell in Which the Schottky barrier is formed with the drain drift region, and a plurality of transistor cells without the Schottky barrier. This permits the transistor cells to be kept very compact. Thus, the mask pattern of step (a) may be narrower over the transistor cells than over the area where the Schottky barrier is formed. The dopant introduced into the transistor cells in step (c) may be laterally scattered and/or diffused to merge into a single channel-accommodating region that extends under the mask pattern in the transistor cells. Additional dopant of the second conductivity type may be introduced into the transistor cells to form a more highly doped contact region for the channel-accommodating region of the transistor cells. This additional dopant is easily masked from the at least one Schottky cell where the drain drift region extends to the body surface to form the Schottky barrier. The mask for the Schottky cell does not require critical alignment.
Synergy is also possible between a me

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