Manufacture of semiconductor device with fine patterns

Details Manufacture of semiconductor device with fine patterns Manufacture of semiconductor device with fine patterns

1998-12-22

2001-02-13

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Chemical etching

Vapor phase etching

C438S636000, C438S637000, C438S643000, C438S669000, C438S685000, C438S700000

Reexamination Certificate

active

06187689

ABSTRACT:

BACKGROUND OF THE INVENTION
a) Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a highly integrated semiconductor device having fine patterns and its manufacturing method.
b) Description of the Related Art
As the integration density of semiconductor integrated circuit devices increases the wiring patterns (inclusive of electrode patterns) are made finer and highly integrated. In order to form intersecting wiring patterns, it is necessary to form a plurality of wiring layers with interlevel or interlayer insulating films being interposed therebetween. In order to form multi-layered wiring patterns, it is necessary to perform photolithography for forming contact holes in insulating layers and for patterning wiring layers.
The following methods (A) to (D) are known as the methods of patterning a wiring or electrode conductive material layer.
(A) As shown in
FIG. 32
, a conductive material layer
3
is formed on an insulating film
2
covering the surface of a semiconductor substrate
1
. A resist film is coated on the conductive material layer
3
, and resist patterns
4
A to
4
C having a desired shape are patterned therefrom by photolithography in a well-known way. By using these resist patterns as a mask, the conductive material layer
3
is selectively dry-etched.
(B) As a patterning mask, a silicon oxide film or silicon nitride having a low etching rate is used (for example, refer to Japanese Patent Laid-open Publication No. 2-125425). Also used as a patterning mask for patterning a polysilicon layer is a laminate of a silicon oxide or silicon nitride film and a resist layer formed thereon (for example, refer to J. S. Maa et al.: J. Vac. Sci. Technol. B9(3), May/June, 1991, pp. 1596-1597).
(C) In coating a resist mask on a high reflectivity substrate, a resist layer mixed with light-absorbing dye is used.
(D) In patterning a conductive material layer formed on a high reflectivity substrate, an antireflection film is coated on the surface of the conductive material layer. As an antireflection film, a silicon nitride film is used (for example, refer to Japanese Patent Laid-open Publications Nos. 1-241125 and 5-55130) or a TiN film is used (for example, refer to Japanese Patent Laid-open Publications Nos. 60-240127, 61-185928, and 63-232432).
A laminate structure of a barrier metal layer, an aluminum layer and an anti-reflection layer such as TiN or amorphous silicon is etched by using resist patterns as a sole mask (P. E. Riley et al.: Solid State Technology February, 1999, pp. 47-55).
When a fine wiring pattern is formed by the method (A), there occurs a phenomenon (the microloading effects of an etching rate) that an etching rate changes with a wiring space (space width).
As shown in
FIG. 32
, in the case of patterns reducing space widths between adjacent pairs of the resist patterns
4
A,
4
B,
4
C, . . . , the etching rate may become lower as the space width is narrowed as shown in FIG.
33
. If the conductive material layer is etched to a predetermined depth at the narrow space width, the layer at the broad space width may be etched excessively and the underlie layer such as the insulating film
2
may be thinned.
In some cases, an etching rate is increased as the space width is narrowed. As shown in
FIG. 34
, in the case of patterns increasing space widths between adjacent pairs of resist patterns
4
a
,
4
b
,
4
c
,
4
d
, . . . , the etching rate may be increased as the space width is narrowed as shown in FIG.
35
. Therefore, if a conductive material layer
3
is etched to a predetermined (depth at the broad space width, the layer at the narrow space width may be etched excessively, and if a selective etching ratio of the underlie layer is low, the underlie layer may be etched as indicated at X
1
and X
2
.
When a fine wiring pattern is formed, there occurs a phenomenon (the microloading effects of a shape of an etched layer) that a shape or size of an etched layer changes with the space width. Such a size change lowers a yield of forming wiring patterns.
Specifically, as shown in
FIG. 36
, if densely distributed wiring patterns
3
P and
3
Q are formed by dry etching by using densely distributed resist patterns
4
P and
4
Q, the width W
D
of the densely distributed wiring pattern
3
P for example may become nearly equal to the width W
O
of the resist pattern
4
P (W
D
, ≅W
O
). In contrast, as shown in
FIG. 37
, if an isolated wiring pattern
3
R is formed by the same dry etching by using an isolated resist pattern
4
R, generally the width W
I
of the isolated wiring pattern
3
R becomes broader than the width W
D
shown in
FIG. 36
(W
I
>W
D
). For the etching of a laminated layer of WSi
2
/polycrystalline silicon, the width exceptionally becomes W
I
<W
D
.
In forming fine wiring patterns, the amount of thinning a film of mask material such as resist increases and the etching selectivity of the mask material (etching ratio of the layer to be etched with respect to the mask) lowers. There is therefore a tendency of lowering a yield of forming wiring patterns.
A film of mask material is thinned during dry etching by collisions of ions or particles having high kinetic energy with the mask material as well as the chemical reaction between gas and the mask material. Collisions of particles having high kinetic energy with the mask material truncate the shoulders of a resist film
4
S as shown in FIG.
38
. The angle of each mask material shoulder takes a value giving the best sputtering efficiency. A real angle is not 45° which gives the best efficiency in purely physical etching. The phenomenon of truncating the shoulders of mask material is called “faceting”, and the plane formed at each shoulder is called a “facet”.
FIG. 39
shows a state where two opposing facets meet each other.
FIG. 38
illustrates a process of forming a wiring layer by dry-etching a conductive material layer
3
by using the resist layer
4
S as a mask. A line width (wiring pattern width) K is set to have a small value approximately equal to the thickness T of the conductive material layer
3
. Even if faceting occurs as shown in
FIG. 38
, the top surface of the resist layer
4
S is left until the right and left facets meet each other. In this case, the amount T
1
of thinning a resist film is equal to that of a resist pattern having a sufficiently large area as compared with the thickness T of the conductive layer
3
to be etched. The sufficiently large area means a large dimension in any in-plane direction of a resist pattern.
This phenomenon becomes more conspicuous as the width of a wiring pattern becomes small. That is to say, an effective selectivity of the wiring pattern to resist lowers more as the wiring pattern becomes narrower.
FIG. 40
shows a dependency upon a line width K of an amount of thinning a resist film, a selection ratio with respect to the resist film, and a resist taper angle &thgr;. As shown in
FIG. 40
, the resist taper angle &thgr; is an angle between a line extended from a facet and a bottom surface of the conductive material layer
3
. Data shown in
FIG. 40
were obtained when aluminum alloy was etched by using BCl
3
/Cl
2
as an etchant gas and a microwave plasma etcher to be described later with reference to FIG.
16
. The data shows that as the line width K becomes narrow, the amount of thinning a resist film increases (the selection ratio of the conductive material to resist lowers) and the resist taper angle &thgr; becomes large.
Although a resist mask used as an etching mask is preferably made thin, a substantial selection ratio wiring patterns with respect to an etching mask lowers as wiring patterns are made fine, as previously described with reference to
FIGS. 38
to
40
. As a result, if a resist layer is made thin, the resist mask may be etched completely during etching and wiring patterns may be broken.
In order to prevent a selection ratio from being lowered as patterns are made fine, it is necessary to develop etching techniques having a high

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