Semiconductor device manufacturing: process – Making device array and selectively interconnecting – Rendering selected devices operable or inoperable
Patent
1994-11-30
1998-12-22
Chaudhari, Chandra
Semiconductor device manufacturing: process
Making device array and selectively interconnecting
Rendering selected devices operable or inoperable
438132, 438601, 438702, 438940, 438717, 438736, 438671, H01L 2128, H01L 2144
Patent
active
058518568
ABSTRACT:
After an insulating film is deposited over metal patterns, a resist film is coated over the whole surface of the insulating film until the surface of the resist film becomes flat. The resist film is removed by reactive ion etching until a partial surface area of the insulating film deposited over the metal patterns is exposed. Another photoresist film is coated on the surface to cover a part of the exposed areas of the insulating film and the resist film, exposed and developed to form a resist mask. The area not covered with the resist mask and the resist film is selectively removed by anisotropic etching. The resist mask and the resist film are removed to obtain a window having a width equal to the width of a convex of the insulating film. A method of manufacturing a semiconductor device that is capable of exposing a metal wiring layer at a high precision is provided.
REFERENCES:
patent: 4518629 (1985-05-01), Jeuch
patent: 4632725 (1986-12-01), Hartmann et al.
patent: 4666553 (1987-05-01), Blumenfeld et al.
patent: 4675984 (1987-06-01), Hsu
patent: 4689112 (1987-08-01), Bersin
patent: 4708720 (1987-11-01), Pasch
patent: 4720620 (1988-01-01), Arima
patent: 4740485 (1988-04-01), Sharpe-Geisler
patent: 4795720 (1989-01-01), Kawanabe
patent: 4829025 (1989-05-01), Iranmanesh
patent: 5021121 (1991-06-01), Groechel et al.
patent: 5096850 (1992-03-01), Lippitt, III
patent: 5139963 (1992-08-01), Suzuki et al.
patent: 5173442 (1992-12-01), Carey
patent: 5466636 (1995-11-01), Cronin et al.
Wolf, Stanley Silicon Processing for the VLSI Era vol. 1, pp 541, 428.
Wolf Stanley Silicon Processing for the VLSI Era, vol. 2, pp 316-318.
Wolf, Stanley, Silicon Processing for the VLSI Era, vol. 2, pp. 180-183, 194-194, 1990.
"Silicon Processing for the VLSI Era", Process Technology, Stanley Wolf, et al, vol. 1, pp. 423-424 (1986).
"Semiconductor Dry Etching Technique", Takashi Tokuyama, et al, pp. 206-218 (1992 Oct.).
"Organometallic Materials in Lithography: A Review", J. Vac. Science Technology, M. Hatzakis, et al, Vo. B.6(6) (1988).
"High Resolution, Steep Profile Resist Patterns", J. Vac. Science Technology,J. M. Moran, et al, Vo. 16(6) (1979).
Chaudhari Chandra
Whipple Matthew
Yamaha Corporation
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