Manufacture of an integrated circuit isolation structure

Details Manufacture of an integrated circuit isolation structure Manufacture of an integrated circuit isolation structure

1999-08-18

2001-11-20

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S437000, C148SDIG005

Reexamination Certificate

active

06319796

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to integrated circuit device manufacture, and more particularly, but not exclusively, relates to techniques to provide electrical isolation structures for an integrated circuit.
Shallow Trench Isolation (STI) is becoming a favored technology to electrically isolate regions of an integrated circuit having components with submicron critical dimensions. Generally, STI involves forming trenches in an integrated circuit substrate, then filling these trenches with a dielectric material. One approach has been to fill the trenches with Tetraethylorthosilicate (TEOS) using a Low Pressure Chemical Vapor Deposition (LPCVD) procedure as described, for example, in U.S. Pat. No. 5,691,215 to Dai et al. However, this approach tends to leave too many voids and other discontinuities as integrated circuits are scaled down to include components having a critical dimension equal to or less than 0.25 microns.
Consequently, other approaches have been investigated. For example, U.S. Pat. No. 5,728,621 to Zheng et al. describes a High Density Plasma (HDP) deposition of a dielectric material to fill isolation trenches. Still, one drawback of this approach is poor local planarity over topography of various sizes and pattern densities. Generally, HDP deposition results in a thicker material over large, expansive features between the trenches, and a thinner material over narrow trenches that may be narrowly spaced from one another. Due to this nonuniformity, subsequent planarization procedures, such as Chemical-Mechanical Polishing (CMP), frequently result in the advertent reduction in the thickness of a layer or film beneath the HDP material in regions where it is thin, or the failure to remove some of the HDP material in regions where it is thick.
One attempt to solve this problem has been a “reverse mask” scheme. This scheme includes placement of a mask over areas where the HDP material is thinner to selectively etch away the thicker regions until a generally uniform HDP material thickness results. The reverse mask is then removed and the device planarized to desired specifications. Unfortunately, the reverse mask process significantly complicates manufacturing, adding several device processing phases. Concomitantly, manufacturing costs generally increase. Thus, there is a demand for better techniques to provide isolation structures.
SUMMARY OF THE INVENTIONS
One form of the present invention is an improved integrated circuit device. An alternative form of the present invention is an improved process for providing an electronic device. This process may include a High Density Plasma (HDP) deposition to facilitate manufacture of an integrated circuit device.
A further alternative form is a technique to provide isolation structures on a device. For instance, this technique may be applied to form isolation structures along a substrate of an integrated circuit device. In another instance, this technique may include an improved process for filling substrate trenches with a dielectric to provide one or more isolation structures.
In another alternative form, the present invention includes forming a number of trenches in a substrate of a workpiece for making at least one integrated circuit. The trenches define a number of regions along the substrate to be electrically isolated from one another. The trenches are at least partially filled by simultaneously depositing and sputter etching a dielectric material with a deposition-to-etch (deposition:etch) ratio of at least about 5. More preferably, the deposition:etch ratio is in a range of about 5.5 to about 6.5. Most preferably, the deposition:etch ratio is in a range of about 5.8 to about 6.2. Further processing of the workpiece may include planarization.
Other alternative forms of the present invention include, but are not limited to, a technique for forming a number of trenches in an integrated circuit substrate that define a number of substrate regions to be electrically isolated from one another. A dielectric material is deposited in the trenches by exposure to a high density plasma having a first deposition-to-etch ratio. The high density plasma is adjusted to a second deposition-to-etch ratio greater than the first ratio to accumulate the dielectric material on the substrate after at least partially filling the trenches. A portion of the dielectric material is removed to planarize the workpiece.
In yet another alternative form, the present invention includes forming a number of trenches in an integrated circuit substrate and depositing a dielectric material in the trenches. The dielectric material may be provided by a high density plasma having a deposition-to-etch ratio of at least about 5. A number of circuit components may be provided along the substrate. In this form, deposition of the dielectric material may include depositing a TEOS dielectric after at least partially filling the trenches with the dielectric material by the high density plasma.
Further alternative forms of the present invention include controlling thickness variation of a coating on a device. This coating may be applied to uniformly fill and ameliorate unevenness of an underlying structure, such as a substrate having one or more trenches.
Still another alternative form includes providing a number of trenches in a workpiece and depositing a dielectric on the workpiece by exposing the workpiece to a high density plasma. The dielectric at least partially fills the trenches. The deposition includes establishing a thickness of the dielectric on the workplace with a maximum step height-to-thickness ratio of about 0.2. During further processing, the workpiece may be planarized by chemical-mechanical polishing.
Further objects, forms, embodiments, benefits, advantages, features, and aspects of the present invention shall become apparent from the description and drawings contained herein.


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