Manufacture of an asymmetric non-volatile memory cell

Details Manufacture of an asymmetric non-volatile memory cell Manufacture of an asymmetric non-volatile memory cell

1993-08-02

1995-07-11

Popek, Joseph A.

Fishing, trapping, and vermin destroying

437 52, 437 48, 365185, H01L 2122

Patent

active

054321069

ABSTRACT:
An EPROM memory cell and its fabrication are described. The semiconductor substrate is a first conductivity type. The process begins by forming a conductive gate overlying the substrate, but electrically insulated therefrom by a layer of a first dielectric material. The gate includes a first conductive material, a second layer of dielectric material, and a second conductive layer. A sidewall dielectric spacer is formed adjacent to an edge of the gate. Ions are implanted into the substrate of a species of an opposite conductivity type, at a substantial acute angle relative to a vertical angle with respect to the substrate, with the spacer protecting the substrate from ion implantation adjacent to the gate. Alternatively, the sidewall can be formed subsequent to the second deposition of doping ions at an acute angle.

REFERENCES:
patent: 4771012 (1988-09-01), Yabu et al.
patent: 5073514 (1991-12-01), Ito et al.
patent: 5147811 (1992-09-01), Sakagami
patent: 5158901 (1992-12-01), Kosa et al.
D. Liu et al, "Optimization of a Source-Side-Injection FAMOS cell for Flash EPROM Applications" IEDM 91 315-318, IEEE (1991).
"114 .mu.m LATID (Large-Tilled-Angle Implanted Drain) Technology" by T. Hori, published in IEDM 89 pp. 777/780.
"Graded-Junction Gage/N-Overlapped LDD MOSFET Structures for High Hot-Carrier Reliability" by U. Okumura et al, published in IEEE.
Transactions on Electron Devices, vol. 38, No. 12, Dec. 1991, pp. 2647-2656.

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