Semiconductor device manufacturing: process – Formation of electrically isolated lateral semiconductive... – Grooved and refilled with deposited dielectric material
Patent
1998-11-27
1999-12-07
Fourson, George
Semiconductor device manufacturing: process
Formation of electrically isolated lateral semiconductive...
Grooved and refilled with deposited dielectric material
438427, H01L 21762
Patent
active
059982799
ABSTRACT:
This is a method of manufacture of a shallow trench isolation semiconductor device with STI trenches where an active area mask is provided for exposure of an active area during manufacture of the device comprises several following steps. The STI trenches are filled by coating the device with a blanket coating of silicon oxide. Coat the device with negative resist. Next, expose the negative resist layer with the active area mask for the device providing windows through the negative photoresist layer with an level of exposure energy provided to broaden the dimensions of exposure substantially laterally of the active area mask. Then, etch back the silicon oxide layer to a thin layer below the windows through the negative photoresist layer. Strip the resist. Finally, perform chemical mechanical planarization to remove excess silicon oxide from the surface.
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patent: 5728618 (1998-03-01), Tseng
Ackerman Stephen B.
Fourson George
Jones II Graham S.
Saile George O.
Vanguard International Semiconductor Corporation
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